582a5237f9
This patch reverts region's scheduling to the original untouched state in case if we have have decreased occupancy. In addition it switches to use TargetRegisterInfo occupancy callback for pressure limits instead of gradually increasing limits which were just passed by. We are going to stay with the best schedule so we do not need to tolerate worsened scheduling anymore. Differential Revision: https://reviews.llvm.org/D29971 llvm-svn: 295206
128 lines
4.9 KiB
LLVM
128 lines
4.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s
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; If spilling to smem, additional registers are used for the resource
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; descriptor.
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; ALL-LABEL: {{^}}max_9_sgprs:
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; ALL: SGPRBlocks: 1
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; ALL: NumSGPRsForWavesPerEU: 9
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define void @max_9_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 addrspace(1)* %out5,
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i32 %one, i32 %two, i32 %three, i32 %four, i32 %five) #0 {
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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store i32 %five, i32 addrspace(1)* %out5
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ret void
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}
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; private resource: 4
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; scratch wave offset: 1
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; workgroup ids: 3
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; dispatch id: 2
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; queue ptr: 2
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; flat scratch init: 2
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; ---------------------
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; total: 14
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; + reserved vcc = 16
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; Because we can't handle re-using the last few input registers as the
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; special vcc etc. registers (as well as decide to not use the unused
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; features when the number of registers is frozen), this ends up using
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; more than expected.
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; ALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:
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; TOSGPR: SGPRBlocks: 1
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; TOSGPR: NumSGPRsForWavesPerEU: 16
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; TOSMEM: s_mov_b64 s[10:11], s[2:3]
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; TOSMEM: s_mov_b64 s[8:9], s[0:1]
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; TOSMEM: s_mov_b32 s7, s13
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; TOSMEM: SGPRBlocks: 1
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; TOSMEM: NumSGPRsForWavesPerEU: 16
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define void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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%x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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%x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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%x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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%x.3 = call i64 @llvm.amdgcn.dispatch.id()
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%x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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%x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()
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store volatile i32 0, i32* undef
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br label %stores
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stores:
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store volatile i32 %x.0, i32 addrspace(1)* undef
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store volatile i32 %x.0, i32 addrspace(1)* undef
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store volatile i32 %x.0, i32 addrspace(1)* undef
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store volatile i64 %x.3, i64 addrspace(1)* undef
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store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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ret void
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}
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; The following test is commented out for now; http://llvm.org/PR31230
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; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}
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; ; Make sure copies for input buffer are not clobbered. This requires
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; ; swapping the order the registers are copied from what normally
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; ; happens.
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; XTOSMEM: s_mov_b32 s5, s11
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; XTOSMEM: s_add_u32 m0, s5,
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; XTOSMEM: s_buffer_store_dword vcc_lo, s[0:3], m0
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; XALL: SGPRBlocks: 2
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; XALL: NumSGPRsForWavesPerEU: 18
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;define void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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; i32 addrspace(1)* %out2,
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; i32 addrspace(1)* %out3,
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; i32 addrspace(1)* %out4,
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; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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; store volatile i32 0, i32* undef
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; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
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; store volatile i64 %x.3, i64 addrspace(1)* undef
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; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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; store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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;
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; store i32 %one, i32 addrspace(1)* %out1
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; store i32 %two, i32 addrspace(1)* %out2
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; store i32 %three, i32 addrspace(1)* %out3
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; store i32 %four, i32 addrspace(1)* %out4
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; ret void
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;}
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declare i32 @llvm.amdgcn.workgroup.id.x() #1
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declare i32 @llvm.amdgcn.workgroup.id.y() #1
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declare i32 @llvm.amdgcn.workgroup.id.z() #1
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declare i64 @llvm.amdgcn.dispatch.id() #1
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declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
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declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #1
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attributes #0 = { nounwind "amdgpu-num-sgpr"="14" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "amdgpu-num-sgpr"="12" }
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attributes #3 = { nounwind "amdgpu-num-sgpr"="11" }
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