582a5237f9
This patch reverts region's scheduling to the original untouched state in case if we have have decreased occupancy. In addition it switches to use TargetRegisterInfo occupancy callback for pressure limits instead of gradually increasing limits which were just passed by. We are going to stay with the best schedule so we do not need to tolerate worsened scheduling anymore. Differential Revision: https://reviews.llvm.org/D29971 llvm-svn: 295206
272 lines
8.2 KiB
LLVM
272 lines
8.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s -check-prefix=FUNC
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; mul24 and mad24 are affected
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; FUNC-LABEL: {{^}}test_mul_v2i32:
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test_mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = mul <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul_v4i32:
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_mul_lo_i32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @v_mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = mul <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_trunc_i64_mul_to_i32:
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; SI: s_load_dword
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; SI: s_load_dword
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; SI: s_mul_i32
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; SI: buffer_store_dword
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define void @s_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%mul = mul i64 %b, %a
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%trunc = trunc i64 %mul to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_trunc_i64_mul_to_i32:
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; SI: s_load_dword
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; SI: s_load_dword
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; SI: v_mul_lo_i32
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; SI: buffer_store_dword
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define void @v_trunc_i64_mul_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%mul = mul i64 %b, %a
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%trunc = trunc i64 %mul to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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; This 64-bit multiply should just use MUL_HI and MUL_LO, since the top
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; 32-bits of both arguments are sign bits.
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; FUNC-LABEL: {{^}}mul64_sext_c:
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; EG-DAG: MULLO_INT
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; EG-DAG: MULHI_INT
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; SI-DAG: s_mul_i32
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; SI-DAG: v_mul_hi_i32
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define void @mul64_sext_c(i64 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = sext i32 %in to i64
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%1 = mul i64 %0, 80
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul64_sext_c:
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; EG-DAG: MULLO_INT
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; EG-DAG: MULHI_INT
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_hi_i32
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; SI: s_endpgm
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define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%ext = sext i32 %val to i64
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%mul = mul i64 %ext, 80
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul64_sext_inline_imm:
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; SI-DAG: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
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; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9
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; SI: s_endpgm
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define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%val = load i32, i32 addrspace(1)* %in, align 4
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%ext = sext i32 %val to i64
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%mul = mul i64 %ext, 9
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_mul_i32:
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; SI: s_load_dword [[SRC0:s[0-9]+]],
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; SI: s_load_dword [[SRC1:s[0-9]+]],
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; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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; SI: s_endpgm
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define void @s_mul_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%mul = mul i32 %a, %b
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store i32 %mul, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul_i32:
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; SI: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @v_mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load i32, i32 addrspace(1)* %in
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%b = load i32, i32 addrspace(1)* %b_ptr
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%result = mul i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; A standard 64-bit multiply. The expansion should be around 6 instructions.
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; It would be difficult to match the expansion correctly without writing
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; a really complicated list of FileCheck expressions. I don't want
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; to confuse people who may 'break' this test with a correct optimization,
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; so this test just uses FUNC-LABEL to make sure the compiler does not
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; crash with a 'failed to select' error.
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; FUNC-LABEL: {{^}}s_mul_i64:
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define void @s_mul_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%mul = mul i64 %a, %b
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul_i64:
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; SI: v_mul_lo_i32
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define void @v_mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%b = load i64, i64 addrspace(1)* %bptr, align 8
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%mul = mul i64 %a, %b
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store i64 %mul, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}mul32_in_branch:
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; SI: s_mul_i32
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define void @mul32_in_branch(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i32, i32 addrspace(1)* %in
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br label %endif
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else:
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%2 = mul i32 %a, %b
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}mul64_in_branch:
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; SI-DAG: s_mul_i32
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; SI-DAG: v_mul_hi_u32
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; SI: s_endpgm
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define void @mul64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64, i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = mul i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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; FIXME: Load dwordx4
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; FUNC-LABEL: {{^}}s_mul_i128:
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI: v_mul_hi_u32
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; SI: v_mul_hi_u32
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; SI: s_mul_i32
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; SI: v_mul_hi_u32
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; SI: s_mul_i32
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; SI: s_mul_i32
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; SI: v_mul_hi_u32
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; SI: v_mul_hi_u32
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; SI: s_mul_i32
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; SI-DAG: s_mul_i32
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; SI-DAG: v_mul_hi_u32
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; SI: s_mul_i32
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; SI: s_mul_i32
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; SI: s_mul_i32
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; SI: s_mul_i32
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; SI: s_mul_i32
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; SI: buffer_store_dwordx4
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define void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b) nounwind #0 {
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%mul = mul i128 %a, %b
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store i128 %mul, i128 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_mul_i128:
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; SI: {{buffer|flat}}_load_dwordx4
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; SI: {{buffer|flat}}_load_dwordx4
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_lo_i32
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; SI: v_add_i32_e32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_hi_u32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_lo_i32
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; SI-DAG: v_mul_lo_i32
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; SI: {{buffer|flat}}_store_dwordx4
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define void @v_mul_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %aptr, i128 addrspace(1)* %bptr) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep.a = getelementptr inbounds i128, i128 addrspace(1)* %aptr, i32 %tid
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%gep.b = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
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%gep.out = getelementptr inbounds i128, i128 addrspace(1)* %bptr, i32 %tid
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%a = load i128, i128 addrspace(1)* %gep.a
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%b = load i128, i128 addrspace(1)* %gep.b
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%mul = mul i128 %a, %b
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store i128 %mul, i128 addrspace(1)* %gep.out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone}
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