269 lines
9.8 KiB
C++
269 lines
9.8 KiB
C++
//===-- X86EncodingOptimization.cpp - X86 Encoding optimization -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the X86 encoding optimization
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//
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//===----------------------------------------------------------------------===//
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#include "X86EncodingOptimization.h"
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#include "X86BaseInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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static bool shouldExchange(const MCInst &MI, unsigned OpIdx1, unsigned OpIdx2) {
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return !X86II::isX86_64ExtendedReg(MI.getOperand(OpIdx1).getReg()) &&
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X86II::isX86_64ExtendedReg(MI.getOperand(OpIdx2).getReg());
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}
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bool X86::optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc) {
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unsigned OpIdx1, OpIdx2;
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unsigned NewOpc;
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unsigned Opcode = MI.getOpcode();
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#define FROM_TO(FROM, TO, IDX1, IDX2) \
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case X86::FROM: \
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NewOpc = X86::TO; \
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OpIdx1 = IDX1; \
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OpIdx2 = IDX2; \
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break;
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#define TO_REV(FROM) FROM_TO(FROM, FROM##_REV, 0, 1)
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switch (MI.getOpcode()) {
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default: {
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// If the instruction is a commutable arithmetic instruction we might be
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// able to commute the operands to get a 2 byte VEX prefix.
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uint64_t TSFlags = Desc.TSFlags;
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if (!Desc.isCommutable() || (TSFlags & X86II::EncodingMask) != X86II::VEX ||
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(TSFlags & X86II::OpMapMask) != X86II::TB ||
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(TSFlags & X86II::FormMask) != X86II::MRMSrcReg ||
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(TSFlags & X86II::REX_W) || !(TSFlags & X86II::VEX_4V) ||
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MI.getNumOperands() != 3)
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return false;
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// These two are not truly commutable.
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if (Opcode == X86::VMOVHLPSrr || Opcode == X86::VUNPCKHPDrr)
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return false;
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OpIdx1 = 1;
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OpIdx2 = 2;
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if (!shouldExchange(MI, OpIdx1, OpIdx2))
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return false;
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std::swap(MI.getOperand(OpIdx1), MI.getOperand(OpIdx2));
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return true;
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}
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// Commute operands to get a smaller encoding by using VEX.R instead of
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// VEX.B if one of the registers is extended, but other isn't.
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FROM_TO(VMOVZPQILo2PQIrr, VMOVPQI2QIrr, 0, 1)
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TO_REV(VMOVAPDrr)
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TO_REV(VMOVAPDYrr)
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TO_REV(VMOVAPSrr)
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TO_REV(VMOVAPSYrr)
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TO_REV(VMOVDQArr)
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TO_REV(VMOVDQAYrr)
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TO_REV(VMOVDQUrr)
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TO_REV(VMOVDQUYrr)
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TO_REV(VMOVUPDrr)
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TO_REV(VMOVUPDYrr)
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TO_REV(VMOVUPSrr)
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TO_REV(VMOVUPSYrr)
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#undef TO_REV
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#define TO_REV(FROM) FROM_TO(FROM, FROM##_REV, 0, 2)
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TO_REV(VMOVSDrr)
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TO_REV(VMOVSSrr)
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#undef TO_REV
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#undef FROM_TO
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}
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if (!shouldExchange(MI, OpIdx1, OpIdx2))
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return false;
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MI.setOpcode(NewOpc);
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return true;
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}
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// NOTE: We may write this as an InstAlias if it's only used by AsmParser. See
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// validateTargetOperandClass.
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bool X86::optimizeShiftRotateWithImmediateOne(MCInst &MI) {
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unsigned NewOpc;
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#define TO_IMM1(FROM) \
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case X86::FROM##i: \
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NewOpc = X86::FROM##1; \
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break;
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switch (MI.getOpcode()) {
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default:
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return false;
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TO_IMM1(RCR8r)
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TO_IMM1(RCR16r)
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TO_IMM1(RCR32r)
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TO_IMM1(RCR64r)
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TO_IMM1(RCL8r)
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TO_IMM1(RCL16r)
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TO_IMM1(RCL32r)
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TO_IMM1(RCL64r)
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TO_IMM1(ROR8r)
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TO_IMM1(ROR16r)
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TO_IMM1(ROR32r)
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TO_IMM1(ROR64r)
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TO_IMM1(ROL8r)
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TO_IMM1(ROL16r)
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TO_IMM1(ROL32r)
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TO_IMM1(ROL64r)
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TO_IMM1(SAR8r)
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TO_IMM1(SAR16r)
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TO_IMM1(SAR32r)
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TO_IMM1(SAR64r)
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TO_IMM1(SHR8r)
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TO_IMM1(SHR16r)
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TO_IMM1(SHR32r)
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TO_IMM1(SHR64r)
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TO_IMM1(SHL8r)
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TO_IMM1(SHL16r)
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TO_IMM1(SHL32r)
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TO_IMM1(SHL64r)
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TO_IMM1(RCR8m)
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TO_IMM1(RCR16m)
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TO_IMM1(RCR32m)
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TO_IMM1(RCR64m)
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TO_IMM1(RCL8m)
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TO_IMM1(RCL16m)
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TO_IMM1(RCL32m)
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TO_IMM1(RCL64m)
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TO_IMM1(ROR8m)
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TO_IMM1(ROR16m)
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TO_IMM1(ROR32m)
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TO_IMM1(ROR64m)
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TO_IMM1(ROL8m)
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TO_IMM1(ROL16m)
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TO_IMM1(ROL32m)
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TO_IMM1(ROL64m)
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TO_IMM1(SAR8m)
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TO_IMM1(SAR16m)
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TO_IMM1(SAR32m)
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TO_IMM1(SAR64m)
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TO_IMM1(SHR8m)
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TO_IMM1(SHR16m)
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TO_IMM1(SHR32m)
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TO_IMM1(SHR64m)
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TO_IMM1(SHL8m)
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TO_IMM1(SHL16m)
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TO_IMM1(SHL32m)
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TO_IMM1(SHL64m)
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#undef TO_IMM1
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}
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MCOperand &LastOp = MI.getOperand(MI.getNumOperands() - 1);
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if (!LastOp.isImm() || LastOp.getImm() != 1)
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return false;
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MI.setOpcode(NewOpc);
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MI.erase(&LastOp);
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return true;
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}
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bool X86::optimizeVPCMPWithImmediateOneOrSix(MCInst &MI) {
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unsigned Opc1;
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unsigned Opc2;
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#define FROM_TO(FROM, TO1, TO2) \
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case X86::FROM: \
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Opc1 = X86::TO1; \
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Opc2 = X86::TO2; \
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break;
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switch (MI.getOpcode()) {
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default:
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return false;
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FROM_TO(VPCMPBZ128rmi, VPCMPEQBZ128rm, VPCMPGTBZ128rm)
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FROM_TO(VPCMPBZ128rmik, VPCMPEQBZ128rmk, VPCMPGTBZ128rmk)
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FROM_TO(VPCMPBZ128rri, VPCMPEQBZ128rr, VPCMPGTBZ128rr)
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FROM_TO(VPCMPBZ128rrik, VPCMPEQBZ128rrk, VPCMPGTBZ128rrk)
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FROM_TO(VPCMPBZ256rmi, VPCMPEQBZ256rm, VPCMPGTBZ256rm)
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FROM_TO(VPCMPBZ256rmik, VPCMPEQBZ256rmk, VPCMPGTBZ256rmk)
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FROM_TO(VPCMPBZ256rri, VPCMPEQBZ256rr, VPCMPGTBZ256rr)
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FROM_TO(VPCMPBZ256rrik, VPCMPEQBZ256rrk, VPCMPGTBZ256rrk)
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FROM_TO(VPCMPBZrmi, VPCMPEQBZrm, VPCMPGTBZrm)
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FROM_TO(VPCMPBZrmik, VPCMPEQBZrmk, VPCMPGTBZrmk)
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FROM_TO(VPCMPBZrri, VPCMPEQBZrr, VPCMPGTBZrr)
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FROM_TO(VPCMPBZrrik, VPCMPEQBZrrk, VPCMPGTBZrrk)
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FROM_TO(VPCMPDZ128rmi, VPCMPEQDZ128rm, VPCMPGTDZ128rm)
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FROM_TO(VPCMPDZ128rmib, VPCMPEQDZ128rmb, VPCMPGTDZ128rmb)
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FROM_TO(VPCMPDZ128rmibk, VPCMPEQDZ128rmbk, VPCMPGTDZ128rmbk)
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FROM_TO(VPCMPDZ128rmik, VPCMPEQDZ128rmk, VPCMPGTDZ128rmk)
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FROM_TO(VPCMPDZ128rri, VPCMPEQDZ128rr, VPCMPGTDZ128rr)
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FROM_TO(VPCMPDZ128rrik, VPCMPEQDZ128rrk, VPCMPGTDZ128rrk)
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FROM_TO(VPCMPDZ256rmi, VPCMPEQDZ256rm, VPCMPGTDZ256rm)
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FROM_TO(VPCMPDZ256rmib, VPCMPEQDZ256rmb, VPCMPGTDZ256rmb)
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FROM_TO(VPCMPDZ256rmibk, VPCMPEQDZ256rmbk, VPCMPGTDZ256rmbk)
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FROM_TO(VPCMPDZ256rmik, VPCMPEQDZ256rmk, VPCMPGTDZ256rmk)
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FROM_TO(VPCMPDZ256rri, VPCMPEQDZ256rr, VPCMPGTDZ256rr)
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FROM_TO(VPCMPDZ256rrik, VPCMPEQDZ256rrk, VPCMPGTDZ256rrk)
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FROM_TO(VPCMPDZrmi, VPCMPEQDZrm, VPCMPGTDZrm)
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FROM_TO(VPCMPDZrmib, VPCMPEQDZrmb, VPCMPGTDZrmb)
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FROM_TO(VPCMPDZrmibk, VPCMPEQDZrmbk, VPCMPGTDZrmbk)
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FROM_TO(VPCMPDZrmik, VPCMPEQDZrmk, VPCMPGTDZrmk)
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FROM_TO(VPCMPDZrri, VPCMPEQDZrr, VPCMPGTDZrr)
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FROM_TO(VPCMPDZrrik, VPCMPEQDZrrk, VPCMPGTDZrrk)
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FROM_TO(VPCMPQZ128rmi, VPCMPEQQZ128rm, VPCMPGTQZ128rm)
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FROM_TO(VPCMPQZ128rmib, VPCMPEQQZ128rmb, VPCMPGTQZ128rmb)
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FROM_TO(VPCMPQZ128rmibk, VPCMPEQQZ128rmbk, VPCMPGTQZ128rmbk)
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FROM_TO(VPCMPQZ128rmik, VPCMPEQQZ128rmk, VPCMPGTQZ128rmk)
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FROM_TO(VPCMPQZ128rri, VPCMPEQQZ128rr, VPCMPGTQZ128rr)
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FROM_TO(VPCMPQZ128rrik, VPCMPEQQZ128rrk, VPCMPGTQZ128rrk)
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FROM_TO(VPCMPQZ256rmi, VPCMPEQQZ256rm, VPCMPGTQZ256rm)
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FROM_TO(VPCMPQZ256rmib, VPCMPEQQZ256rmb, VPCMPGTQZ256rmb)
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FROM_TO(VPCMPQZ256rmibk, VPCMPEQQZ256rmbk, VPCMPGTQZ256rmbk)
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FROM_TO(VPCMPQZ256rmik, VPCMPEQQZ256rmk, VPCMPGTQZ256rmk)
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FROM_TO(VPCMPQZ256rri, VPCMPEQQZ256rr, VPCMPGTQZ256rr)
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FROM_TO(VPCMPQZ256rrik, VPCMPEQQZ256rrk, VPCMPGTQZ256rrk)
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FROM_TO(VPCMPQZrmi, VPCMPEQQZrm, VPCMPGTQZrm)
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FROM_TO(VPCMPQZrmib, VPCMPEQQZrmb, VPCMPGTQZrmb)
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FROM_TO(VPCMPQZrmibk, VPCMPEQQZrmbk, VPCMPGTQZrmbk)
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FROM_TO(VPCMPQZrmik, VPCMPEQQZrmk, VPCMPGTQZrmk)
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FROM_TO(VPCMPQZrri, VPCMPEQQZrr, VPCMPGTQZrr)
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FROM_TO(VPCMPQZrrik, VPCMPEQQZrrk, VPCMPGTQZrrk)
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FROM_TO(VPCMPWZ128rmi, VPCMPEQWZ128rm, VPCMPGTWZ128rm)
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FROM_TO(VPCMPWZ128rmik, VPCMPEQWZ128rmk, VPCMPGTWZ128rmk)
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FROM_TO(VPCMPWZ128rri, VPCMPEQWZ128rr, VPCMPGTWZ128rr)
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FROM_TO(VPCMPWZ128rrik, VPCMPEQWZ128rrk, VPCMPGTWZ128rrk)
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FROM_TO(VPCMPWZ256rmi, VPCMPEQWZ256rm, VPCMPGTWZ256rm)
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FROM_TO(VPCMPWZ256rmik, VPCMPEQWZ256rmk, VPCMPGTWZ256rmk)
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FROM_TO(VPCMPWZ256rri, VPCMPEQWZ256rr, VPCMPGTWZ256rr)
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FROM_TO(VPCMPWZ256rrik, VPCMPEQWZ256rrk, VPCMPGTWZ256rrk)
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FROM_TO(VPCMPWZrmi, VPCMPEQWZrm, VPCMPGTWZrm)
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FROM_TO(VPCMPWZrmik, VPCMPEQWZrmk, VPCMPGTWZrmk)
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FROM_TO(VPCMPWZrri, VPCMPEQWZrr, VPCMPGTWZrr)
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FROM_TO(VPCMPWZrrik, VPCMPEQWZrrk, VPCMPGTWZrrk)
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#undef FROM_TO
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}
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MCOperand &LastOp = MI.getOperand(MI.getNumOperands() - 1);
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int64_t Imm = LastOp.getImm();
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unsigned NewOpc;
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if (Imm == 0)
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NewOpc = Opc1;
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else if(Imm == 6)
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NewOpc = Opc2;
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else
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return false;
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MI.setOpcode(NewOpc);
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MI.erase(&LastOp);
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return true;
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}
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bool X86::optimizeMOVSX(MCInst &MI) {
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unsigned NewOpc;
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#define FROM_TO(FROM, TO, R0, R1) \
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case X86::FROM: \
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if (MI.getOperand(0).getReg() != X86::R0 || \
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MI.getOperand(1).getReg() != X86::R1) \
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return false; \
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NewOpc = X86::TO; \
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break;
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switch (MI.getOpcode()) {
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default:
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return false;
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FROM_TO(MOVSX16rr8, CBW, AX, AL) // movsbw %al, %ax --> cbtw
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FROM_TO(MOVSX32rr16, CWDE, EAX, AX) // movswl %ax, %eax --> cwtl
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FROM_TO(MOVSX64rr32, CDQE, RAX, EAX) // movslq %eax, %rax --> cltq
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}
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MI.clear();
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MI.setOpcode(NewOpc);
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return true;
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}
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