eb86de63d9
Currently, we specify that the ptrmask intrinsic allows the mask to have any size, which will be zero-extended or truncated to the pointer size. However, what semantics of the specified GEP expansion actually imply is that the mask is only meaningful up to the pointer type *index* size -- any higher bits of the pointer will always be preserved. In other words, the mask gets 1-extended from the index size to the pointer size. This is also the behavior we want for CHERI architectures. This PR makes two changes: * It spells out the interaction with the pointer type index size more explicitly. * It requires that the mask matches the pointer type index size. The intention here is to make handling of this intrinsic more robust, to avoid accidental mix-ups of pointer size and index size in code generating this intrinsic. If a zero-extend or truncate of the mask is desired, it should just be done explicitly in IR. This also cuts down on the amount of testing we have to do, and things transforms needs to check for. As far as I can tell, we don't actually support pointers with different index type size at the SDAG level, so I'm just asserting the sizes match there for now. Out-of-tree targets using different index sizes may need to adjust that code.
106 lines
4.5 KiB
LLVM
106 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt < %s -passes=infer-alignment -S | FileCheck %s
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target datalayout = "p1:64:64:64:32-p2:64:64:64:128"
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; ------------------------------------------------------------------------------
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; load instructions
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; ------------------------------------------------------------------------------
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define void @load(ptr align 1 %ptr) {
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; CHECK-LABEL: define void @load
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; CHECK-SAME: (ptr align 1 [[PTR:%.*]]) {
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; CHECK-NEXT: [[ALIGNED_0:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -2)
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; CHECK-NEXT: [[ALIGNED_1:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -4)
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; CHECK-NEXT: [[ALIGNED_2:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -8)
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; CHECK-NEXT: [[LOAD_0:%.*]] = load <16 x i8>, ptr [[ALIGNED_0]], align 2
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; CHECK-NEXT: [[LOAD_1:%.*]] = load <16 x i8>, ptr [[ALIGNED_1]], align 4
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; CHECK-NEXT: [[LOAD_2:%.*]] = load <16 x i8>, ptr [[ALIGNED_2]], align 8
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; CHECK-NEXT: ret void
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;
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%aligned.0 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -2)
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%aligned.1 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -4)
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%aligned.2 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -8)
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%load.0 = load <16 x i8>, ptr %aligned.0, align 1
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%load.1 = load <16 x i8>, ptr %aligned.1, align 1
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%load.2 = load <16 x i8>, ptr %aligned.2, align 1
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ret void
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}
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; ------------------------------------------------------------------------------
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; store instructions
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; ------------------------------------------------------------------------------
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define void @store(ptr align 1 %ptr) {
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; CHECK-LABEL: define void @store
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; CHECK-SAME: (ptr align 1 [[PTR:%.*]]) {
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; CHECK-NEXT: [[ALIGNED_0:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -2)
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; CHECK-NEXT: [[ALIGNED_1:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -4)
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; CHECK-NEXT: [[ALIGNED_2:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -8)
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; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[ALIGNED_0]], align 2
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; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[ALIGNED_1]], align 4
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; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[ALIGNED_2]], align 8
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; CHECK-NEXT: ret void
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;
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%aligned.0 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -2)
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%aligned.1 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -4)
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%aligned.2 = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -8)
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store <16 x i8> zeroinitializer, ptr %aligned.0, align 1
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store <16 x i8> zeroinitializer, ptr %aligned.1, align 1
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store <16 x i8> zeroinitializer, ptr %aligned.2, align 1
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ret void
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}
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; ------------------------------------------------------------------------------
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; Overaligned pointer
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; ------------------------------------------------------------------------------
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; Underlying alignment greater than alignment forced by ptrmask
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define void @ptrmask_overaligned(ptr align 16 %ptr) {
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; CHECK-LABEL: define void @ptrmask_overaligned
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; CHECK-SAME: (ptr align 16 [[PTR:%.*]]) {
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; CHECK-NEXT: [[ALIGNED:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR]], i64 -8)
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; CHECK-NEXT: [[LOAD:%.*]] = load <16 x i8>, ptr [[ALIGNED]], align 16
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; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[ALIGNED]], align 16
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; CHECK-NEXT: ret void
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;
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%aligned = call ptr @llvm.ptrmask.p0.i64(ptr %ptr, i64 -8)
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%load = load <16 x i8>, ptr %aligned, align 1
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store <16 x i8> zeroinitializer, ptr %aligned, align 1
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ret void
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}
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define i8 @smaller_index_type(ptr addrspace(1) %ptr) {
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; CHECK-LABEL: define i8 @smaller_index_type
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; CHECK-SAME: (ptr addrspace(1) [[PTR:%.*]]) {
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; CHECK-NEXT: [[PTR2:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i32(ptr addrspace(1) [[PTR]], i32 -4)
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; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(1) [[PTR2]], align 4
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; CHECK-NEXT: ret i8 [[LOAD]]
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;
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%ptr2 = call ptr addrspace(1) @llvm.ptrmask.p1.i32(ptr addrspace(1) %ptr, i32 -4)
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%load = load i8, ptr addrspace(1) %ptr2, align 1
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ret i8 %load
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}
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define i8 @larger_index_type(ptr addrspace(2) %ptr) {
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; CHECK-LABEL: define i8 @larger_index_type
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; CHECK-SAME: (ptr addrspace(2) [[PTR:%.*]]) {
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; CHECK-NEXT: [[PTR2:%.*]] = call ptr addrspace(2) @llvm.ptrmask.p2.i128(ptr addrspace(2) [[PTR]], i128 -4)
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; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(2) [[PTR2]], align 4
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; CHECK-NEXT: ret i8 [[LOAD]]
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;
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%ptr2 = call ptr addrspace(2) @llvm.ptrmask.p2.i128(ptr addrspace(2) %ptr, i128 -4)
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%load = load i8, ptr addrspace(2) %ptr2, align 1
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ret i8 %load
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}
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declare ptr @llvm.ptrmask.p0.i64(ptr, i64)
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declare ptr addrspace(1) @llvm.ptrmask.p1.i32(ptr addrspace(1), i32)
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declare ptr addrspace(2) @llvm.ptrmask.p2.i128(ptr addrspace(2), i128)
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