882c43d703
Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68993 llvm-svn: 375084
86 lines
3.2 KiB
C++
86 lines
3.2 KiB
C++
//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
|
|
#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
|
|
|
|
#include "AMDGPUFrameLowering.h"
|
|
|
|
namespace llvm {
|
|
|
|
class SIInstrInfo;
|
|
class SIMachineFunctionInfo;
|
|
class SIRegisterInfo;
|
|
class GCNSubtarget;
|
|
|
|
class SIFrameLowering final : public AMDGPUFrameLowering {
|
|
public:
|
|
SIFrameLowering(StackDirection D, Align StackAl, int LAO,
|
|
unsigned TransAl = 1)
|
|
: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
|
|
~SIFrameLowering() override = default;
|
|
|
|
void emitEntryFunctionPrologue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const;
|
|
void emitPrologue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const override;
|
|
void emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const override;
|
|
int getFrameIndexReference(const MachineFunction &MF, int FI,
|
|
unsigned &FrameReg) const override;
|
|
|
|
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
|
|
RegScavenger *RS = nullptr) const override;
|
|
void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs,
|
|
RegScavenger *RS = nullptr) const;
|
|
bool
|
|
assignCalleeSavedSpillSlots(MachineFunction &MF,
|
|
const TargetRegisterInfo *TRI,
|
|
std::vector<CalleeSavedInfo> &CSI) const override;
|
|
|
|
bool isSupportedStackID(TargetStackID::Value ID) const override;
|
|
|
|
void processFunctionBeforeFrameFinalized(
|
|
MachineFunction &MF,
|
|
RegScavenger *RS = nullptr) const override;
|
|
|
|
MachineBasicBlock::iterator
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const override;
|
|
|
|
private:
|
|
void emitFlatScratchInit(const GCNSubtarget &ST,
|
|
MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const;
|
|
|
|
unsigned getReservedPrivateSegmentBufferReg(
|
|
const GCNSubtarget &ST,
|
|
const SIInstrInfo *TII,
|
|
const SIRegisterInfo *TRI,
|
|
SIMachineFunctionInfo *MFI,
|
|
MachineFunction &MF) const;
|
|
|
|
std::pair<unsigned, bool> getReservedPrivateSegmentWaveByteOffsetReg(
|
|
const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
|
|
SIMachineFunctionInfo *MFI, MachineFunction &MF) const;
|
|
|
|
// Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
|
|
void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
|
|
MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
|
|
MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
|
|
unsigned ScratchRsrcReg) const;
|
|
|
|
public:
|
|
bool hasFP(const MachineFunction &MF) const override;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
|