599591f3d4
Add vector MSA register classes to fprb, they are 128 bit wide. MSA instructions use the same registers for both integer and floating point operations. Therefore we only need to check for vector element size during legalization or instruction selection. Add helper function in MipsLegalizerInfo and switch to legalIf LegalizeRuleSet to keep legalization rules compact since they depend on MipsSubtarget and presence of MSA. fprb is assigned to all vector operands. Move selectLoadStoreOpCode to MipsInstructionSelector in order to reduce number of arguments. Differential Revision: https://reviews.llvm.org/D68867 llvm-svn: 374872
314 lines
9.9 KiB
C++
314 lines
9.9 KiB
C++
//===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for Mips.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MipsLegalizerInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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using namespace llvm;
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struct TypesAndMemOps {
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LLT ValTy;
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LLT PtrTy;
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unsigned MemSize;
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bool MustBeNaturallyAligned;
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};
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static bool
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CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
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std::initializer_list<TypesAndMemOps> SupportedValues) {
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for (auto &Val : SupportedValues) {
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if (Val.ValTy != Query.Types[0])
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continue;
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if (Val.PtrTy != Query.Types[1])
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continue;
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if (Val.MemSize != Query.MMODescrs[0].SizeInBits)
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continue;
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if (Val.MustBeNaturallyAligned &&
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Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
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continue;
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return true;
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}
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return false;
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}
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MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT s1 = LLT::scalar(1);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
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.lowerFor({{s32, s1}});
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getActionDefinitionsBuilder(G_UMULH)
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.legalFor({s32})
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.maxScalar(0, s32);
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},
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{s32, p0, 16, ST.hasMips32r6()},
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{s32, p0, 32, ST.hasMips32r6()},
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{p0, p0, 32, ST.hasMips32r6()},
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{s64, p0, 64, ST.hasMips32r6()}}))
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return true;
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if (ST.hasMSA() &&
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CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},
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{v8s16, p0, 128, false},
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{v4s32, p0, 128, false},
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{v2s64, p0, 128, false}}))
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return true;
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return false;
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})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_IMPLICIT_DEF)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder(G_UNMERGE_VALUES)
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.legalFor({{s32, s64}});
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getActionDefinitionsBuilder(G_MERGE_VALUES)
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.legalFor({{s64, s32}});
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getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_TRUNC)
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(1, s32);
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getActionDefinitionsBuilder(G_SELECT)
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.legalForCartesianProduct({p0, s32, s64}, {s32})
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.minScalar(0, s32)
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_BRCOND)
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.legalFor({s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_BRJT)
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.legalFor({{p0, s32}});
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getActionDefinitionsBuilder(G_BRINDIRECT)
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.legalFor({p0});
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getActionDefinitionsBuilder(G_PHI)
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.legalFor({p0, s32, s64})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
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.legalFor({s32})
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.minScalar(0, s32)
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.libcallFor({s64});
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getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
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.legalFor({{s32, s32}})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_ICMP)
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.legalForCartesianProduct({s32}, {s32, p0})
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.clampScalar(1, s32, s32)
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_CONSTANT)
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_GEP, G_INTTOPTR})
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.legalFor({{p0, s32}});
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalFor({{s32, p0}});
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getActionDefinitionsBuilder(G_FRAME_INDEX)
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.legalFor({p0});
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getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
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.legalFor({p0});
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getActionDefinitionsBuilder(G_DYN_STACKALLOC)
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.lowerFor({{p0, s32}});
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getActionDefinitionsBuilder(G_VASTART)
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.legalFor({p0});
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
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.legalFor({s32, s64});
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getActionDefinitionsBuilder(G_FCMP)
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.legalFor({{s32, s32}, {s32, s64}})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
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.libcallFor({s32, s64});
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getActionDefinitionsBuilder(G_FPEXT)
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.legalFor({{s64, s32}});
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getActionDefinitionsBuilder(G_FPTRUNC)
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.legalFor({{s32, s64}});
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// FP to int conversion instructions
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getActionDefinitionsBuilder(G_FPTOSI)
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.legalForCartesianProduct({s32}, {s64, s32})
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.libcallForCartesianProduct({s64}, {s64, s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_FPTOUI)
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.libcallForCartesianProduct({s64}, {s64, s32})
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.lowerForCartesianProduct({s32}, {s64, s32})
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.minScalar(0, s32);
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// Int to FP conversion instructions
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getActionDefinitionsBuilder(G_SITOFP)
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.legalForCartesianProduct({s64, s32}, {s32})
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.libcallForCartesianProduct({s64, s32}, {s64})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_UITOFP)
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.libcallForCartesianProduct({s64, s32}, {s64})
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.customForCartesianProduct({s64, s32}, {s32})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_SEXT_INREG).lower();
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computeTables();
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verify(*ST.getInstrInfo());
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}
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bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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switch (MI.getOpcode()) {
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case G_UITOFP: {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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LLT SrcTy = MRI.getType(Src);
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if (SrcTy != s32)
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return false;
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if (DstTy != s32 && DstTy != s64)
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return false;
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// Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
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// unsigned to double. Mantissa has 52 bits so we use following trick:
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// First make floating point bit mask 0x43300000ABCDEFGH.
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// Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
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// Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
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// Done. Trunc double to float if needed.
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MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
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STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
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{Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
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Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
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s64, BitsToDouble(UINT64_C(0x4330000000000000)));
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if (DstTy == s64)
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MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
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else {
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MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
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MIRBuilder.buildFPTrunc(Dst, ResF64);
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}
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MI.eraseFromParent();
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break;
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}
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default:
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return false;
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}
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return true;
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}
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bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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const MipsSubtarget &ST =
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static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
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const MipsInstrInfo &TII = *ST.getInstrInfo();
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const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
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const RegisterBankInfo &RBI = *ST.getRegBankInfo();
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MIRBuilder.setInstr(MI);
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switch (MI.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memset:
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case Intrinsic::memmove:
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if (createMemLibcall(MIRBuilder, MRI, MI) ==
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LegalizerHelper::UnableToLegalize)
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return false;
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MI.eraseFromParent();
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return true;
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case Intrinsic::trap: {
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MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
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MI.eraseFromParent();
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return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
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}
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case Intrinsic::vacopy: {
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Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
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MachinePointerInfo MPO;
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MIRBuilder.buildLoad(Tmp, MI.getOperand(2),
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*MI.getMF()->getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad, 4, 4));
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MIRBuilder.buildStore(Tmp, MI.getOperand(1),
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*MI.getMF()->getMachineMemOperand(
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MPO, MachineMemOperand::MOStore, 4, 4));
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MI.eraseFromParent();
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return true;
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}
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default:
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break;
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}
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return true;
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}
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