c4d256a590
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
57 lines
1.7 KiB
LLVM
57 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}i1_copy_from_loop:
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;
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; SI: [[LOOP:BB0_[0-9]+]]: ; %Flow1
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; SI: s_or_b64 exec, exec, [[EXIT_MASK:s\[[0-9]+:[0-9]+\]]]
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; SI: ; %Flow
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; SI: s_and_b64 [[ACCUM_MASK:s\[[0-9]+:[0-9]+\]]], [[CC_MASK:s\[[0-9]+:[0-9]+\]]], exec
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; SI: s_or_b64 [[I1_VALUE:s\[[0-9]+:[0-9]+\]]], s[6:7], [[ACCUM_MASK]]
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; SI: s_cbranch_execz [[FOR_END_LABEL:BB0_[0-9]+]]
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; SI: ; %for.body
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; SI: v_cmp_lt_u32_e64 [[CC_MASK]], s{{[0-9]+}}, 4
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; SI: [[FOR_END_LABEL]]
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; SI: s_or_b64 exec, exec, [[EXIT_MASK]]
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; SI: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[I1_VALUE]]
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; SI: s_cbranch_execz [[EXIT:BB0_[0-9]+]]
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; SI: [[EXIT]]
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; SI-NEXT: s_endpgm
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define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) {
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entry:
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br label %for.body
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for.body:
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%i = phi i32 [0, %entry], [%i.inc, %end.loop]
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%cc = icmp ult i32 %i, 4
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br i1 %cc, label %mid.loop, label %for.end
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mid.loop:
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%v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i1 false, i1 false)
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%cc2 = fcmp oge float %v, 0.0
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br i1 %cc2, label %end.loop, label %for.end
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end.loop:
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%i.inc = add i32 %i, 1
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br label %for.body
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for.end:
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br i1 %cc, label %if, label %end
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if:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true)
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br label %end
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end:
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ret void
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}
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declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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attributes #0 = { nounwind readonly }
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attributes #1 = { nounwind inaccessiblememonly }
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