e6f313b380
The default promotion for the add_sat/sub_sat nodes currently does:
ANY_EXTEND iN to iM
SHL by M-N
[US][ADD|SUB]SAT
L/ASHR by M-N
If the promoted add_sat or sub_sat node is not legal, this can produce code
that effectively does a lot of shifting (and requiring large constants to be
materialised) just to use the overflow flag. It is simpler to just do the
saturation manually, using the higher bitwidth addition and a min/max against
the saturating bounds. That is what this patch attempts to do.
Differential Revision: https://reviews.llvm.org/D68926
llvm-svn: 375211
344 lines
10 KiB
LLVM
344 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
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declare i4 @llvm.sadd.sat.i4(i4, i4)
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declare i8 @llvm.sadd.sat.i8(i8, i8)
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declare i16 @llvm.sadd.sat.i16(i16, i16)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i64 @llvm.sadd.sat.i64(i64, i64)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-T1-LABEL: func:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: movs r3, #1
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: mov r1, r3
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; CHECK-T1-NEXT: bmi .LBB0_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r1, #0
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; CHECK-T1-NEXT: .LBB0_2:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: bne .LBB0_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: lsls r1, r3, #31
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; CHECK-T1-NEXT: cmp r0, r2
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; CHECK-T1-NEXT: bvs .LBB0_5
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; CHECK-T1-NEXT: b .LBB0_6
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; CHECK-T1-NEXT: .LBB0_4:
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; CHECK-T1-NEXT: ldr r1, .LCPI0_0
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; CHECK-T1-NEXT: cmp r0, r2
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; CHECK-T1-NEXT: bvc .LBB0_6
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; CHECK-T1-NEXT: .LBB0_5:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB0_6:
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.7:
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; CHECK-T1-NEXT: .LCPI0_0:
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; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK-T2-LABEL: func:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: adds r2, r0, r1
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; CHECK-T2-NEXT: mov.w r3, #0
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; CHECK-T2-NEXT: mov.w r1, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r1, #-2147483648
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; CHECK-T2-NEXT: cmp r2, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r1, r2
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; CHECK-T2-NEXT: mov r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: adds r2, r0, r1
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; CHECK-ARM-NEXT: mov r3, #0
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; CHECK-ARM-NEXT: movwmi r3, #1
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; CHECK-ARM-NEXT: mov r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r3, #0
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; CHECK-ARM-NEXT: mvnne r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r2, r0
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; CHECK-ARM-NEXT: movvc r1, r2
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; CHECK-ARM-NEXT: mov r0, r1
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; CHECK-T1-LABEL: func2:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-T1-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-T1-NEXT: .pad #4
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; CHECK-T1-NEXT: sub sp, #4
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; CHECK-T1-NEXT: str r2, [sp] @ 4-byte Spill
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: movs r4, #1
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; CHECK-T1-NEXT: movs r0, #0
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; CHECK-T1-NEXT: cmp r3, #0
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; CHECK-T1-NEXT: mov r5, r4
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; CHECK-T1-NEXT: bge .LBB1_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r5, r0
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; CHECK-T1-NEXT: .LBB1_2:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: mov r7, r4
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; CHECK-T1-NEXT: bge .LBB1_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: mov r7, r0
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; CHECK-T1-NEXT: .LBB1_4:
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; CHECK-T1-NEXT: subs r6, r7, r5
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; CHECK-T1-NEXT: rsbs r5, r6, #0
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; CHECK-T1-NEXT: adcs r5, r6
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; CHECK-T1-NEXT: ldr r6, [sp] @ 4-byte Reload
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; CHECK-T1-NEXT: adds r6, r2, r6
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; CHECK-T1-NEXT: adcs r1, r3
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: mov r2, r4
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; CHECK-T1-NEXT: bge .LBB1_6
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; CHECK-T1-NEXT: @ %bb.5:
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; CHECK-T1-NEXT: mov r2, r0
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; CHECK-T1-NEXT: .LBB1_6:
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; CHECK-T1-NEXT: subs r0, r7, r2
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; CHECK-T1-NEXT: subs r2, r0, #1
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; CHECK-T1-NEXT: sbcs r0, r2
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; CHECK-T1-NEXT: ands r5, r0
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; CHECK-T1-NEXT: beq .LBB1_8
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; CHECK-T1-NEXT: @ %bb.7:
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; CHECK-T1-NEXT: asrs r6, r1, #31
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; CHECK-T1-NEXT: .LBB1_8:
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; CHECK-T1-NEXT: cmp r1, #0
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; CHECK-T1-NEXT: bmi .LBB1_10
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; CHECK-T1-NEXT: @ %bb.9:
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; CHECK-T1-NEXT: lsls r2, r4, #31
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; CHECK-T1-NEXT: cmp r5, #0
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; CHECK-T1-NEXT: beq .LBB1_11
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; CHECK-T1-NEXT: b .LBB1_12
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; CHECK-T1-NEXT: .LBB1_10:
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; CHECK-T1-NEXT: ldr r2, .LCPI1_0
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; CHECK-T1-NEXT: cmp r5, #0
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; CHECK-T1-NEXT: bne .LBB1_12
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; CHECK-T1-NEXT: .LBB1_11:
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; CHECK-T1-NEXT: mov r2, r1
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; CHECK-T1-NEXT: .LBB1_12:
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; CHECK-T1-NEXT: mov r0, r6
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; CHECK-T1-NEXT: mov r1, r2
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; CHECK-T1-NEXT: add sp, #4
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; CHECK-T1-NEXT: pop {r4, r5, r6, r7, pc}
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.13:
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; CHECK-T1-NEXT: .LCPI1_0:
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; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; CHECK-T2-LABEL: func2:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: cmp.w r1, #-1
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it gt
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; CHECK-T2-NEXT: movgt.w lr, #1
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; CHECK-T2-NEXT: adds r0, r0, r2
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; CHECK-T2-NEXT: adc.w r2, r1, r3
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; CHECK-T2-NEXT: movs r1, #0
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; CHECK-T2-NEXT: cmp.w r2, #-1
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; CHECK-T2-NEXT: it gt
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; CHECK-T2-NEXT: movgt r1, #1
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; CHECK-T2-NEXT: subs.w r1, lr, r1
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; CHECK-T2-NEXT: mov.w r12, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: movne r1, #1
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; CHECK-T2-NEXT: cmp.w r3, #-1
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; CHECK-T2-NEXT: it gt
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; CHECK-T2-NEXT: movgt.w r12, #1
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; CHECK-T2-NEXT: sub.w r3, lr, r12
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; CHECK-T2-NEXT: clz r3, r3
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; CHECK-T2-NEXT: lsrs r3, r3, #5
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; CHECK-T2-NEXT: ands r3, r1
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; CHECK-T2-NEXT: mov.w r1, #-2147483648
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: asrne r0, r2, #31
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; CHECK-T2-NEXT: cmp r2, #0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: mvnmi r1, #-2147483648
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: it eq
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; CHECK-T2-NEXT: moveq r1, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM-LABEL: func2:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: .save {r11, lr}
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; CHECK-ARM-NEXT: push {r11, lr}
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; CHECK-ARM-NEXT: adds r0, r0, r2
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; CHECK-ARM-NEXT: mov r2, #0
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; CHECK-ARM-NEXT: adc r12, r1, r3
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; CHECK-ARM-NEXT: cmn r1, #1
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; CHECK-ARM-NEXT: mov r1, #0
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; CHECK-ARM-NEXT: mov lr, #0
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; CHECK-ARM-NEXT: movwgt r1, #1
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; CHECK-ARM-NEXT: cmn r12, #1
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; CHECK-ARM-NEXT: movwgt r2, #1
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; CHECK-ARM-NEXT: subs r2, r1, r2
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; CHECK-ARM-NEXT: movwne r2, #1
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; CHECK-ARM-NEXT: cmn r3, #1
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; CHECK-ARM-NEXT: movwgt lr, #1
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; CHECK-ARM-NEXT: sub r1, r1, lr
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; CHECK-ARM-NEXT: clz r1, r1
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; CHECK-ARM-NEXT: lsr r1, r1, #5
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; CHECK-ARM-NEXT: ands r2, r1, r2
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; CHECK-ARM-NEXT: asrne r0, r12, #31
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; CHECK-ARM-NEXT: mov r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r12, #0
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; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
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; CHECK-ARM-NEXT: cmp r2, #0
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; CHECK-ARM-NEXT: moveq r1, r12
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; CHECK-ARM-NEXT: pop {r11, pc}
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%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
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ret i64 %tmp
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}
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define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
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; CHECK-T1-LABEL: func16:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: ldr r1, .LCPI2_0
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: blt .LBB2_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB2_2:
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; CHECK-T1-NEXT: ldr r1, .LCPI2_1
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bgt .LBB2_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB2_4:
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.5:
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; CHECK-T1-NEXT: .LCPI2_0:
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; CHECK-T1-NEXT: .long 32767 @ 0x7fff
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; CHECK-T1-NEXT: .LCPI2_1:
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; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
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;
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; CHECK-T2-LABEL: func16:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: movw r1, #32767
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it lt
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; CHECK-T2-NEXT: movlt r1, r0
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; CHECK-T2-NEXT: movw r0, #32768
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; CHECK-T2-NEXT: cmn.w r1, #32768
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; CHECK-T2-NEXT: movt r0, #65535
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; CHECK-T2-NEXT: it gt
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; CHECK-T2-NEXT: movgt r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func16:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: movw r1, #32767
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; CHECK-ARM-NEXT: cmp r0, r1
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; CHECK-ARM-NEXT: movlt r1, r0
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; CHECK-ARM-NEXT: movw r0, #32768
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; CHECK-ARM-NEXT: movt r0, #65535
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; CHECK-ARM-NEXT: cmn r1, #32768
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; CHECK-ARM-NEXT: movgt r0, r1
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
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ret i16 %tmp
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}
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define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
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; CHECK-T1-LABEL: func8:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: movs r1, #127
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; CHECK-T1-NEXT: cmp r0, #127
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; CHECK-T1-NEXT: blt .LBB3_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB3_2:
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; CHECK-T1-NEXT: mvns r1, r1
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bgt .LBB3_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB3_4:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func8:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: cmp r0, #127
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; CHECK-T2-NEXT: it ge
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; CHECK-T2-NEXT: movge r0, #127
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; CHECK-T2-NEXT: cmn.w r0, #128
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; CHECK-T2-NEXT: it le
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; CHECK-T2-NEXT: mvnle r0, #127
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func8:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: cmp r0, #127
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; CHECK-ARM-NEXT: movge r0, #127
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; CHECK-ARM-NEXT: cmn r0, #128
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; CHECK-ARM-NEXT: mvnle r0, #127
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
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ret i8 %tmp
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}
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define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
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; CHECK-T1-LABEL: func3:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: movs r1, #7
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; CHECK-T1-NEXT: cmp r0, #7
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; CHECK-T1-NEXT: blt .LBB4_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB4_2:
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; CHECK-T1-NEXT: mvns r1, r1
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; CHECK-T1-NEXT: cmp r0, r1
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; CHECK-T1-NEXT: bgt .LBB4_4
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: .LBB4_4:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func3:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: cmp r0, #7
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; CHECK-T2-NEXT: it ge
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; CHECK-T2-NEXT: movge r0, #7
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; CHECK-T2-NEXT: cmn.w r0, #8
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; CHECK-T2-NEXT: it le
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; CHECK-T2-NEXT: mvnle r0, #7
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func3:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: cmp r0, #7
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; CHECK-ARM-NEXT: movge r0, #7
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; CHECK-ARM-NEXT: cmn r0, #8
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; CHECK-ARM-NEXT: mvnle r0, #7
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; CHECK-ARM-NEXT: bx lr
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%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
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ret i4 %tmp
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}
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