8a3d7c9cbd
Quite a while ago, we implemented a pass that will reduce the number of CR-logical operations we emit. It does so by converting a CR-logical operation into a branch. We have kept this off by default because it seemed to cause a significant regression with one benchmark. However, that regression turned out to be due to a completely unrelated reason - AADB introducing a self-copy that is a priority-setting nop and it was just exacerbated by this pass. Now that we understand the reason for the only degradation, we can turn this pass on by default. We have long since fixed the cause for the degradation. Differential revision: https://reviews.llvm.org/D52431 llvm-svn: 375152
289 lines
8.1 KiB
LLVM
289 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \
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; RUN: -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr7 \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=NOP8VEC
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define <16 x i8> @getsmaxi8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: getsmaxi8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmaxsb 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxi8:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vmaxsb 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp sgt <16 x i8> %a, %b
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%1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %1
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}
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define <8 x i16> @getsmaxi16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: getsmaxi16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmaxsh 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxi16:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vmaxsh 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp sgt <8 x i16> %a, %b
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%1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <4 x i32> @getsmaxi32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: getsmaxi32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmaxsw 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxi32:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vmaxsw 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp sgt <4 x i32> %a, %b
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%1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: getsmaxi64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmaxsd 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxi64:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xxswapd 0, 35
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; NOP8VEC-NEXT: addi 3, 1, -32
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; NOP8VEC-NEXT: addi 4, 1, -48
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; NOP8VEC-NEXT: xxswapd 1, 34
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; NOP8VEC-NEXT: stxvd2x 0, 0, 3
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; NOP8VEC-NEXT: stxvd2x 1, 0, 4
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; NOP8VEC-NEXT: ld 3, -24(1)
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; NOP8VEC-NEXT: ld 4, -40(1)
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; NOP8VEC-NEXT: ld 6, -48(1)
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; NOP8VEC-NEXT: cmpd 4, 3
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; NOP8VEC-NEXT: li 3, 0
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; NOP8VEC-NEXT: li 4, -1
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; NOP8VEC-NEXT: isel 5, 4, 3, 1
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; NOP8VEC-NEXT: std 5, -8(1)
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; NOP8VEC-NEXT: ld 5, -32(1)
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; NOP8VEC-NEXT: cmpd 6, 5
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; NOP8VEC-NEXT: isel 3, 4, 3, 1
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; NOP8VEC-NEXT: std 3, -16(1)
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; NOP8VEC-NEXT: addi 3, 1, -16
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; NOP8VEC-NEXT: lxvd2x 0, 0, 3
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; NOP8VEC-NEXT: xxswapd 36, 0
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; NOP8VEC-NEXT: xxsel 34, 35, 34, 36
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp sgt <2 x i64> %a, %b
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%1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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define <4 x float> @getsmaxf32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: getsmaxf32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvmaxsp 34, 34, 35
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxf32:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xvmaxsp 34, 34, 35
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; NOP8VEC-NEXT: blr
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entry:
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%0 = fcmp fast oge <4 x float> %a, %b
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%1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <2 x double> @getsmaxf64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: getsmaxf64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvmaxdp 34, 34, 35
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmaxf64:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xvmaxdp 34, 34, 35
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; NOP8VEC-NEXT: blr
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entry:
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%0 = fcmp fast oge <2 x double> %a, %b
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%1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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define <16 x i8> @getsmini8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: getsmini8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vminsb 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmini8:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vminsb 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp slt <16 x i8> %a, %b
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%1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %1
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}
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define <8 x i16> @getsmini16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: getsmini16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vminsh 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmini16:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vminsh 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp slt <8 x i16> %a, %b
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%1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <4 x i32> @getsmini32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: getsmini32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vminsw 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmini32:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: vminsw 2, 2, 3
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp slt <4 x i32> %a, %b
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%1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: getsmini64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vminsd 2, 2, 3
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsmini64:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xxswapd 0, 35
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; NOP8VEC-NEXT: addi 3, 1, -32
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; NOP8VEC-NEXT: addi 4, 1, -48
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; NOP8VEC-NEXT: xxswapd 1, 34
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; NOP8VEC-NEXT: stxvd2x 0, 0, 3
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; NOP8VEC-NEXT: stxvd2x 1, 0, 4
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; NOP8VEC-NEXT: ld 3, -24(1)
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; NOP8VEC-NEXT: ld 4, -40(1)
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; NOP8VEC-NEXT: ld 6, -48(1)
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; NOP8VEC-NEXT: cmpd 4, 3
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; NOP8VEC-NEXT: li 3, 0
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; NOP8VEC-NEXT: li 4, -1
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; NOP8VEC-NEXT: isel 5, 4, 3, 0
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; NOP8VEC-NEXT: std 5, -8(1)
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; NOP8VEC-NEXT: ld 5, -32(1)
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; NOP8VEC-NEXT: cmpd 6, 5
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; NOP8VEC-NEXT: isel 3, 4, 3, 0
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; NOP8VEC-NEXT: std 3, -16(1)
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; NOP8VEC-NEXT: addi 3, 1, -16
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; NOP8VEC-NEXT: lxvd2x 0, 0, 3
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; NOP8VEC-NEXT: xxswapd 36, 0
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; NOP8VEC-NEXT: xxsel 34, 35, 34, 36
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; NOP8VEC-NEXT: blr
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entry:
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%0 = icmp slt <2 x i64> %a, %b
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%1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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define <4 x float> @getsminf32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: getsminf32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvminsp 34, 34, 35
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsminf32:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xvminsp 34, 34, 35
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; NOP8VEC-NEXT: blr
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entry:
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%0 = fcmp fast ole <4 x float> %a, %b
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%1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <2 x double> @getsminf64(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: getsminf64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvmindp 34, 34, 35
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: getsminf64:
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; NOP8VEC: # %bb.0: # %entry
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; NOP8VEC-NEXT: xvmindp 34, 34, 35
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; NOP8VEC-NEXT: blr
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entry:
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%0 = fcmp fast ole <2 x double> %a, %b
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%1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
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; CHECK-LABEL: invalidv1i128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mfvsrd 3, 36
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; CHECK-NEXT: xxswapd 0, 36
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; CHECK-NEXT: mfvsrd 4, 34
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; CHECK-NEXT: xxswapd 1, 34
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; CHECK-NEXT: cmpld 4, 3
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; CHECK-NEXT: cmpd 1, 4, 3
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; CHECK-NEXT: mfvsrd 3, 0
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; CHECK-NEXT: crandc 20, 4, 2
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; CHECK-NEXT: mfvsrd 4, 1
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; CHECK-NEXT: cmpld 1, 4, 3
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; CHECK-NEXT: bc 12, 20, .LBB12_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: crand 20, 2, 4
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; CHECK-NEXT: bc 12, 20, .LBB12_3
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; CHECK-NEXT: # %bb.2:
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; CHECK-NEXT: vmr 2, 4
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; CHECK-NEXT: .LBB12_3:
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; CHECK-NEXT: xxswapd 0, 34
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; CHECK-NEXT: mfvsrd 4, 34
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; CHECK-NEXT: mfvsrd 3, 0
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; CHECK-NEXT: blr
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;
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; NOP8VEC-LABEL: invalidv1i128:
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; NOP8VEC: # %bb.0:
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; NOP8VEC-NEXT: cmpld 4, 8
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; NOP8VEC-NEXT: cmpd 1, 4, 8
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; NOP8VEC-NEXT: addi 5, 1, -32
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; NOP8VEC-NEXT: crandc 20, 4, 2
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; NOP8VEC-NEXT: cmpld 1, 3, 7
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; NOP8VEC-NEXT: crand 21, 2, 4
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; NOP8VEC-NEXT: cror 20, 21, 20
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; NOP8VEC-NEXT: isel 3, 3, 7, 20
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; NOP8VEC-NEXT: isel 4, 4, 8, 20
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; NOP8VEC-NEXT: std 3, -32(1)
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; NOP8VEC-NEXT: addi 3, 1, -16
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; NOP8VEC-NEXT: std 4, -24(1)
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; NOP8VEC-NEXT: lxvd2x 0, 0, 5
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; NOP8VEC-NEXT: stxvd2x 0, 0, 3
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; NOP8VEC-NEXT: ld 3, -16(1)
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; NOP8VEC-NEXT: ld 4, -8(1)
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; NOP8VEC-NEXT: blr
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%1 = icmp slt <2 x i128> %v1, %v2
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%2 = select <2 x i1> %1, <2 x i128> %v1, <2 x i128> %v2
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%3 = extractelement <2 x i128> %2, i32 0
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ret i128 %3
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}
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