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clang-p2996/llvm/lib/Target/AMDGPU
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Brox Chen bf388f8a43 [AMDGPU][True16][CodeGen] legalize operands when move16bit SALU to VALU (#133985) 
This is a follow up PR from
https://github.com/llvm/llvm-project/pull/132089.

When a V2S copy and its useMI are lowered to VALU,  this patch check:
If the generated new VALU is a true16 inst. Add subreg access on all
operands if necessary.

an example MIR looks like:
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:sreg_32 = COPY %1:vgpr_32
%3:sreg_32 = S_FLOOR_F16 %2:sreg_32, ...
```
currently lowered to
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:vgpr_16 = V_FLOOR_F16_t16_e64 0, %1:vgpr_32, 0, 0, 0 ...
```
after this patch
```
%1:vgpr_32 = V_CVT_F32_U32_e64 %0:vgpr_32, 0, 0 ...
%2:vgpr_16 = V_FLOOR_F16_t16_e64 0, %1.lo16:vgpr_32, 0, 0, 0 ...
```
2025-04-03 12:26:41 -04:00
..
AsmParser
[AMDGPU] Hoist some constant stuff out of the loop in AMDGPUAsmParser.cpp. NFC. (#133398)
2025-03-28 03:27:16 -07:00
Disassembler
[AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (#130038)
2025-03-19 07:35:09 +01:00
MCA
[AMDGPU] Insert before and after instructions that always use GDS (#131338)
2025-03-21 09:33:04 +00:00
MCTargetDesc
[MC] Don't print () around $ names
2025-03-30 16:38:16 -07:00
TargetInfo
…
Utils
[NFC][AMDGPU] clang-format AMDGPUBaseInfo.[h,cpp] (#133559)
2025-03-29 10:28:34 -04:00
AMDGPU.h
[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM (#130064)
2025-04-02 16:28:05 +05:30
AMDGPU.td
[AMDGPU] Use a target feature to enable __builtin_amdgcn_global_load_lds on gfx9/10 (#133055)
2025-04-02 20:00:09 +02:00
AMDGPUAliasAnalysis.cpp
[AMDGPU] Fix spurious NoAlias results (#122309)
2025-01-20 14:19:30 +00:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)
2025-03-14 14:21:44 -04:00
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Preserve all analyses if nothing changed (#117994)
2024-11-28 14:33:05 +00:00
AMDGPUArgumentUsageInfo.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUArgumentUsageInfo.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUAsanInstrumentation.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUAsanInstrumentation.h
…
AMDGPUAsmPrinter.cpp
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
AMDGPUAsmPrinter.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
AMDGPUAtomicOptimizer.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUAttributes.def
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
AMDGPUAttributor.cpp
AMDGPU: Fix attributor not handling all trap intrinsics (#131758)
2025-03-19 10:17:28 +07:00
AMDGPUCallingConv.td
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
AMDGPUCallLowering.cpp
[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)
2025-03-20 08:38:04 +01:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
Revert "[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable" (#133880)
2025-04-01 17:37:02 +08:00
AMDGPUCombine.td
[AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (#131307)
2025-03-17 10:26:51 +01:00
AMDGPUCombinerHelper.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUCombinerHelper.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUCtorDtorLowering.cpp
AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)
2024-10-09 18:03:35 +04:00
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
…
AMDGPUExportKernelRuntimeHandles.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUExportKernelRuntimeHandles.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUFeatures.td
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
2024-11-18 10:48:56 -08:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (#117260)
2024-11-22 20:12:50 -08:00
AMDGPUGlobalISelDivergenceLowering.cpp
AMDGPU/GlobalISel: Temporal divergence lowering i1 (#124299)
2025-03-12 12:15:00 +01:00
AMDGPUGlobalISelUtils.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUGlobalISelUtils.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUIGroupLP.cpp
[AMDGPU] Fix a warning
2025-01-11 13:06:37 -08:00
AMDGPUIGroupLP.h
…
AMDGPUImageIntrinsicOptimizer.cpp
[AMDGPU] Change placeholder from undef to poison (#130853)
2025-03-12 12:52:38 +00:00
AMDGPUInsertDelayAlu.cpp
[llvm] Use *Set::insert_range (NFC) (#132509)
2025-03-22 08:07:33 -07:00
AMDGPUInstCombineIntrinsic.cpp
[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)
2025-04-02 19:51:40 +02:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)
2025-03-20 08:38:04 +01:00
AMDGPUInstructions.td
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
2024-11-21 08:51:58 -08:00
AMDGPUInstructionSelector.cpp
[AMDGPU] Use a target feature to enable __builtin_amdgcn_global_load_lds on gfx9/10 (#133055)
2025-04-02 20:00:09 +02:00
AMDGPUInstructionSelector.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
2025-03-17 09:13:20 +01:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
2025-03-17 09:13:20 +01:00
AMDGPUISelLowering.cpp
[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)
2025-04-02 19:51:40 +02:00
AMDGPUISelLowering.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPULateCodeGenPrepare.cpp
[AMDGPU] Whitelist all intrinsics (#130150)
2025-03-06 15:39:11 -08:00
AMDGPULegalizerInfo.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPULegalizerInfo.h
[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)
2025-03-19 16:08:08 +01:00
AMDGPULibCalls.cpp
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
AMDGPULibFunc.cpp
[AMDGPU] Provide default value in get intrinsic param type (#122448)
2025-01-10 15:29:42 +01:00
AMDGPULibFunc.h
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
AMDGPULowerBufferFatPointers.cpp
[AMDGPULowerBufferFatPointers] Use InstSimplifyFolder during rewrites (#134137)
2025-04-03 10:12:18 -05:00
AMDGPULowerKernelArguments.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Add a new function getIntegerPairAttribute (#133271)
2025-03-27 15:38:54 -04:00
AMDGPULowerModuleLDSPass.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUMachineFunction.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMachineFunction.h
…
AMDGPUMachineModuleInfo.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
AMDGPUMarkLastScratchLoad.cpp
[AMDGPU][NPM] Port AMDGPUMarkLastScratchLoad to NPM (#131738)
2025-03-19 09:27:05 +05:30
AMDGPUMCInstLower.cpp
Move relocation specifiers to AMDGPUMCExpr::Specifier
2025-03-30 12:12:38 -07:00
AMDGPUMCInstLower.h
[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#127673)
2025-02-18 18:16:23 -05:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] Debug dump for AMDGPU resource usage (#122952)
2025-03-04 18:15:33 +00:00
AMDGPUMCResourceInfo.h
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
AMDGPUMemoryUtils.cpp
[AMDGPU] Remove unused s_barrier_{init,join,leave} instructions (#129548)
2025-03-04 17:52:43 +01:00
AMDGPUMemoryUtils.h
[AMDGPU] modify named barrier builtins and intrinsics (#114550)
2024-11-06 10:37:22 -08:00
AMDGPUMIRFormatter.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMIRFormatter.h
…
AMDGPUPassRegistry.def
[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM (#130064)
2025-04-02 16:28:05 +05:30
AMDGPUPerfHintAnalysis.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUPredicateControl.td
…
AMDGPUPreLegalizerCombiner.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUPreloadKernArgProlog.cpp
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPreloadKernArgProlog.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPrintfRuntimeBinding.cpp
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
2025-01-21 00:32:56 +09:00
AMDGPUPromoteAlloca.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPURegBankLegalize.cpp
AMDGPU/GlobalISel: Update divergence lowering tests (#128702)
2025-03-12 11:26:52 +01:00
AMDGPURegBankLegalizeHelper.cpp
AMDGPU/GlobalISel: Update divergence lowering tests (#128702)
2025-03-12 11:26:52 +01:00
AMDGPURegBankLegalizeHelper.h
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
AMDGPURegBankLegalizeRules.cpp
AMDGPU/GlobalISel: Update divergence lowering tests (#128702)
2025-03-12 11:26:52 +01:00
AMDGPURegBankLegalizeRules.h
AMDGPU/GlobalISel: Update divergence lowering tests (#128702)
2025-03-12 11:26:52 +01:00
AMDGPURegBankSelect.cpp
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
AMDGPURegisterBankInfo.cpp
[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)
2025-04-02 19:51:40 +02:00
AMDGPURegisterBankInfo.h
…
AMDGPURegisterBanks.td
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
2025-02-25 17:09:34 -05:00
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPURemoveIncompatibleFunctions.h
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPUReserveWWMRegs.cpp
[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)
2025-03-10 17:36:35 +05:30
AMDGPUReserveWWMRegs.h
[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)
2025-03-10 17:36:35 +05:30
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
AMDGPURewriteOutArguments.cpp
[AMDGPU] Avoid repeated hash lookups (NFC) (#128458)
2025-02-23 23:42:30 -08:00
AMDGPURewriteUndefForPHI.cpp
…
AMDGPUSearchableTables.td
[AMDGPU] Add llvm.amdgcn.dead intrinsic (#123190)
2025-02-20 09:25:48 +01:00
AMDGPUSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSetWavePriority.cpp
[AMDGPU] AMDGPUSetWavePriority: Remove unused variable NFC (#134069)
2025-04-02 16:52:05 +05:30
AMDGPUSplitModule.cpp
[EquivalenceClasses] Use SmallVector for deterministic iteration order. (#134075)
2025-04-02 20:27:43 +01:00
AMDGPUSplitModule.h
…
AMDGPUSubtarget.cpp
[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)
2025-03-14 14:21:44 -04:00
AMDGPUSubtarget.h
[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)
2025-03-14 14:21:44 -04:00
AMDGPUSwLowerLDS.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUTargetMachine.cpp
[AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM (#130064)
2025-04-02 16:28:05 +05:30
AMDGPUTargetMachine.h
[AMDGPU][NewPM] Port AMDGPUInsertDelayAlu to NPM (#128003)
2025-02-26 09:50:09 +05:30
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
2025-02-04 08:18:24 +01:00
AMDGPUTargetTransformInfo.h
AMDGPU: Reduce readfirstlane for single demanded vector element (#128647)
2025-03-05 08:35:56 +07:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] Don't unify divergent exit nodes with musttail calls (#126395)
2025-02-09 21:48:24 -05:00
AMDGPUUnifyDivergentExitNodes.h
…
AMDGPUUnifyMetadata.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
AMDGPUWaitSGPRHazards.cpp
[AMDGPU] Merge consecutive wait_alu instruction (#128916)
2025-03-12 10:27:27 +01:00
AMDGPUWaitSGPRHazards.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU][GFX11] buffer_load_lds_{size} instructions do not exist (#132916)
2025-03-25 15:24:06 +01:00
CaymanInstructions.td
…
CMakeLists.txt
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
DSDIRInstructions.td
[AMDGPU] New GFX12 aliases lds_direct_load and lds_param_load (#119205)
2024-12-09 14:15:56 +00:00
DSInstructions.td
[AMDGPU][True16][CodeGen] D16 LDS load/store pseudo instructions in true16 (#131427)
2025-03-17 10:28:45 -04:00
EvergreenInstructions.td
…
EXPInstructions.td
…
FLATInstructions.td
AMDGPU: Remove some overrides of SubtargetPredicate on real instructions (#129668)
2025-03-04 17:00:08 +07:00
GCNCreateVOPD.cpp
[AMDGPU][NPM] Port GCNCreateVOPD to NPM (#130059)
2025-03-14 10:22:45 +05:30
GCNDPPCombine.cpp
[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)
2025-03-31 10:18:25 -04:00
GCNDPPCombine.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
GCNHazardRecognizer.cpp
[AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)
2025-03-14 12:31:57 -04:00
GCNHazardRecognizer.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
GCNILPSched.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
GCNIterativeScheduler.cpp
[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)
2024-10-09 09:54:11 -07:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
GCNNSAReassign.cpp
[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)
2025-02-18 11:13:31 +05:30
GCNNSAReassign.h
[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)
2025-02-18 11:13:31 +05:30
GCNPreRALongBranchReg.cpp
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRALongBranchReg.h
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRAOptimizations.cpp
[AMDGPU][True16][CodeGen] update test for buildbot failure (#131028)
2025-03-12 16:59:48 -04:00
GCNPreRAOptimizations.h
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
GCNProcessors.td
[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)
2025-02-19 10:20:48 +01:00
GCNRegPressure.cpp
[AMDGPU] Avoid repeated hash lookups (NFC) (#132511)
2025-03-21 22:15:40 -07:00
GCNRegPressure.h
[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)
2025-01-22 09:11:22 -08:00
GCNRewritePartialRegUses.cpp
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
GCNRewritePartialRegUses.h
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
GCNSchedStrategy.cpp
[Target] Use *Set::insert_range (NFC) (#132140)
2025-03-20 09:09:30 -07:00
GCNSchedStrategy.h
[AMDGPU] - Fix non-deterministic compile issue (#126271)
2025-02-10 07:58:02 +00:00
GCNSubtarget.cpp
[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)
2025-03-14 14:21:44 -04:00
GCNSubtarget.h
[AMDGPU] Use a target feature to enable __builtin_amdgcn_global_load_lds on gfx9/10 (#133055)
2025-04-02 20:00:09 +02:00
GCNVOPDUtils.cpp
…
GCNVOPDUtils.h
…
InstCombineTables.td
…
MIMGInstructions.td
[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)
2025-03-19 16:08:08 +01:00
R600.h
…
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
R600FrameLowering.cpp
…
R600FrameLowering.h
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
R600InstrFormats.td
…
R600InstrInfo.cpp
[MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)
2025-03-20 07:24:53 -07:00
R600InstrInfo.h
[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)
2025-02-24 09:55:34 -08:00
R600InstrInfo.td
…
R600Instructions.td
…
R600ISelDAGToDAG.cpp
…
R600ISelLowering.cpp
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
2025-01-21 00:32:56 +09:00
R600ISelLowering.h
…
R600MachineCFGStructurizer.cpp
[Target] Use *Set::insert_range (NFC) (#132879)
2025-03-24 22:42:04 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600OpenCLImageTypeLoweringPass.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
R600OptimizeVectorRegisters.cpp
[AMDGPU] Avoid repeated hash lookups (NFC) (#127445)
2025-02-16 23:24:15 -08:00
R600Packetizer.cpp
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
R600Processors.td
[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)
2024-09-30 10:29:31 +01:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600Subtarget.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600TargetMachine.cpp
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
R600TargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
R600TargetTransformInfo.cpp
…
R600TargetTransformInfo.h
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
AMDGPU: Rename variable from undef to poison (#130460)
2025-03-10 22:18:36 +07:00
SIDefines.h
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIFixSGPRCopies.cpp
AMDGPU: Move insertion into V2SCopies map (#130776)
2025-03-18 23:28:49 +07:00
SIFixSGPRCopies.h
…
SIFixVGPRCopies.cpp
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFixVGPRCopies.h
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFoldOperands.cpp
[AMDGPU][True16][CodeGen] fold clamp update for true16 (#128919)
2025-04-02 17:10:53 -04:00
SIFoldOperands.h
AMDGPU: Implement getRequiredProperties for SIFoldOperands (#127522)
2025-02-18 08:22:45 +07:00
SIFormMemoryClauses.cpp
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
SIFormMemoryClauses.h
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
SIFrameLowering.cpp
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIFrameLowering.h
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIInsertHardClauses.cpp
[AMDGPU][NPM] Port SIInsertHardClauses to NPM (#130062)
2025-03-25 15:33:32 +05:30
SIInsertWaitcnts.cpp
[AMDGPU] Relax lds dma waitcnt with no aliasing pair (#131842)
2025-03-24 10:38:47 -07:00
SIInstrFormats.td
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
2024-11-21 08:51:58 -08:00
SIInstrInfo.cpp
[AMDGPU][True16][CodeGen] legalize operands when move16bit SALU to VALU (#133985)
2025-04-03 12:26:41 -04:00
SIInstrInfo.h
[AMDGPU][True16][CodeGen] legalize operands when move16bit SALU to VALU (#133985)
2025-04-03 12:26:41 -04:00
SIInstrInfo.td
[AMDGPU][True16][CodeGen] update VGPRimm for t16 (#131021)
2025-03-20 14:46:29 -04:00
SIInstructions.td
[AMDGPU][True16][CodeGen] remove v2i16 from srl pattern (#133458)
2025-03-28 18:48:08 -04:00
SIISelLowering.cpp
[AMDGPU] Use a target feature to enable __builtin_amdgcn_global_load_lds on gfx9/10 (#133055)
2025-04-02 20:00:09 +02:00
SIISelLowering.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
SILateBranchLowering.cpp
[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)
2025-03-26 19:28:19 +05:30
SILoadStoreOptimizer.cpp
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
SILoadStoreOptimizer.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
SILowerControlFlow.cpp
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerControlFlow.h
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerI1Copies.cpp
[AMDGPU] Use MapVector instead of DenseMap (NFC) (#133356)
2025-03-27 20:34:23 -07:00
SILowerI1Copies.h
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
SILowerSGPRSpills.cpp
[AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (#129848)
2025-03-18 10:51:07 +05:30
SILowerSGPRSpills.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
SILowerWWMCopies.cpp
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SILowerWWMCopies.h
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SIMachineFunctionInfo.cpp
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIMachineFunctionInfo.h
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIMachineScheduler.cpp
[AMDGPU] Avoid repeated map lookups (NFC) (#132877)
2025-03-24 22:41:27 -07:00
SIMachineScheduler.h
[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC
2025-01-26 00:26:00 -08:00
SIMemoryLegalizer.cpp
[AMDGPU][NPM] Port SIMemoryLegalizer to NPM (#130060)
2025-03-12 14:30:35 +05:30
SIModeRegister.cpp
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
2025-03-04 10:51:03 +05:30
SIModeRegisterDefaults.cpp
…
SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (#128928)
2025-02-28 09:41:05 -05:00
SIOptimizeExecMasking.h
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
SIOptimizeExecMaskingPreRA.h
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
SIOptimizeVGPRLiveRange.cpp
[AMDGPU][SIOptimizeVGPRLiveRange] Add setpreservesCFG in the legacy pass flow. (#118256)
2024-12-02 23:16:03 +05:30
SIOptimizeVGPRLiveRange.h
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
SIPeepholeSDWA.cpp
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
SIPeepholeSDWA.h
…
SIPostRABundler.cpp
[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
2025-02-21 16:05:58 +05:30
SIPostRABundler.h
[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
2025-02-21 16:05:58 +05:30
SIPreAllocateWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
SIPreAllocateWWMRegs.h
[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)
2024-10-22 15:37:08 +05:30
SIPreEmitPeephole.cpp
[AMDGPU][SIPreEmitPeephole] Fix mustRetainExeczBranch (#120121)
2024-12-17 11:47:38 +01:00
SIProgramInfo.cpp
[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)
2025-03-17 23:17:46 +00:00
SIProgramInfo.h
[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)
2025-03-17 23:17:46 +00:00
SIRegisterInfo.cpp
[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)
2025-03-19 13:49:19 +01:00
SIRegisterInfo.h
[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)
2025-03-12 16:12:58 -04:00
SIRegisterInfo.td
[AMDGPU] 4-align TTMP triples (#132759)
2025-03-24 17:11:39 +00:00
SISchedule.td
[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)
2025-02-19 10:20:48 +01:00
SIShrinkInstructions.cpp
[AMDGPU] Unused sdst writing to null (#133229)
2025-03-28 18:12:34 +01:00
SIShrinkInstructions.h
…
SIWholeQuadMode.cpp
[AMDGCN][SIWholeQuadMode] Rework splitBlock/lowerKillI1/lowerKillF32 to handle case when SI_KILL_I1_TERMINATOR -1 0 is not the unique terminator
2025-03-24 15:57:08 +01:00
SIWholeQuadMode.h
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
SMInstructions.td
[AMDGPU] Disallow null for more resource operands (#121941)
2025-01-08 08:02:10 +00:00
SOPInstructions.td
[AMDGPU] (x or y) xor -1 -> x nor y (#130264)
2025-03-28 11:20:17 +01:00
VIInstrFormats.td
…
VINTERPInstructions.td
[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)
2024-12-09 11:52:05 -05:00
VOP1Instructions.td
[AMDGPU][True16][CodeGen] Implement sgpr folding in true16 (#128929)
2025-04-02 16:08:26 -04:00
VOP2Instructions.td
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
VOP3Instructions.td
[AMDGPU] Add subtarget feature for v_lshl_add_u64. NFC. (#133723)
2025-03-31 16:25:00 +01:00
VOP3PInstructions.td
AMDGPU: Sort an instruction definition by opcode (#129350)
2025-03-01 11:10:36 +07:00
VOPCInstructions.td
[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (#125561)
2025-02-05 10:40:34 -05:00
VOPDInstructions.td
[AMDGPU] Add GFX12 assembler/disassembler support for v_dual_dot2acc_* (#119211)
2024-12-09 15:12:08 +00:00
VOPInstructions.td
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00