e9a3ea2218
This PR instruments the optimization passes in the SystemZ backend with calls to `MachineFunction::substituteDebugValuesForInst` where instruction substitutions are made to instructions that may compute tracked values. Tests are also added for each of the substitutions that were inserted. Details on the individual passes follow. ### systemz-copy-physregs When a copy targets an access register, we redirect the copy via an auxiliary register. This leads to the final result being written by a newly inserted SAR instruction, rather than the original MI, so we need to update the debug value tracking to account for this. ### systemz-long-branch This pass relaxes relative branch instructions based on the actual locations of blocks. Only one of the branch instructions qualifies for debug value tracking: BRCT, i.e. branch-relative-on-count, which subtracts 1 from a register and branches if the result is not zero. This is relaxed into an add-immediate and a conditional branch, so any `debug-instr-number` present must move to the add-immediate instruction. ### systemz-post-rewrite This pass replaces `LOCRMux` and `SELRMux` pseudoinstructions with either the real versions of those instructions, or with branching programs that implement the intent of the Pseudo. In all these cases, any `debug-instr-number` attached to the pseudo needs to be reallocated to the appropriate instruction in the result, either LOCR, SELR, or a COPY. ### systemz-elim-compare Similar to systemz-long-branch, for this pass, only few substitutions are necessary, since it mainly deals with conditional branch instructions. The only exceptiona are again branch-relative-on-count, as it modifies a counter as part of the instruction, as well as any of the load instructions that are affected.
115 lines
3.7 KiB
C++
115 lines
3.7 KiB
C++
//===---------- SystemZPhysRegCopy.cpp - Handle phys reg copies -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass makes sure that a COPY of a physical register will be
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// implementable after register allocation in copyPhysReg() (this could be
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// done in EmitInstrWithCustomInserter() instead if COPY instructions would
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// be passed to it).
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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namespace {
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class SystemZCopyPhysRegs : public MachineFunctionPass {
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public:
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static char ID;
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SystemZCopyPhysRegs()
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: MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
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initializeSystemZCopyPhysRegsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool visitMBB(MachineBasicBlock &MBB);
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const SystemZInstrInfo *TII;
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MachineRegisterInfo *MRI;
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};
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char SystemZCopyPhysRegs::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(SystemZCopyPhysRegs, "systemz-copy-physregs",
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"SystemZ Copy Physregs", false, false)
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FunctionPass *llvm::createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM) {
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return new SystemZCopyPhysRegs();
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}
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void SystemZCopyPhysRegs::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool SystemZCopyPhysRegs::visitMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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// Certain special registers can only be copied from a subset of the
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// default register class of the type. It is therefore necessary to create
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// the target copy instructions before regalloc instead of in copyPhysReg().
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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MBBI != E; ) {
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MachineInstr *MI = &*MBBI++;
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if (!MI->isCopy())
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continue;
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DebugLoc DL = MI->getDebugLoc();
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Register SrcReg = MI->getOperand(1).getReg();
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Register DstReg = MI->getOperand(0).getReg();
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if (DstReg.isVirtual() &&
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(SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) {
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Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
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if (SrcReg == SystemZ::CC)
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BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp);
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else
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BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg);
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MI->getOperand(1).setReg(Tmp);
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Modified = true;
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}
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else if (SrcReg.isVirtual() &&
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SystemZ::AR32BitRegClass.contains(DstReg)) {
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Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass);
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MI->getOperand(0).setReg(Tmp);
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MachineInstr *NMI =
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BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp);
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// SAR now writes the final value to DstReg, so update debug values.
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MBB.getParent()->substituteDebugValuesForInst(*MI, *NMI);
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Modified = true;
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}
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}
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return Modified;
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}
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bool SystemZCopyPhysRegs::runOnMachineFunction(MachineFunction &F) {
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TII = F.getSubtarget<SystemZSubtarget>().getInstrInfo();
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MRI = &F.getRegInfo();
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bool Modified = false;
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for (auto &MBB : F)
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Modified |= visitMBB(MBB);
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return Modified;
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}
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