The operand order of the assembly for dmr extract instructions has changed since they were added. The results now come before the uses.
48 lines
1.9 KiB
LLVM
48 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=future -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=future -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
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define void @v1024ls(ptr nocapture readonly %vqp, ptr nocapture %resp) {
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; CHECK-LABEL: v1024ls:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp34, 0(r3)
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; CHECK-NEXT: lxvp vsp36, 32(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-NEXT: lxvp vsp34, 64(r3)
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; CHECK-NEXT: lxvp vsp36, 96(r3)
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; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-NEXT: stxvp vsp34, 96(r4)
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; CHECK-NEXT: stxvp vsp36, 64(r4)
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; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-NEXT: stxvp vsp34, 32(r4)
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; CHECK-NEXT: stxvp vsp36, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: v1024ls:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvp vsp34, 96(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 64(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc_hi0, vsp36, vsp34, 1
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; CHECK-BE-NEXT: lxvp vsp34, 32(r3)
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; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
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; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
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; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
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; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
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; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
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; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <1024 x i1>, ptr %vqp, align 64
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store <1024 x i1> %0, ptr %resp, align 64
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ret void
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}
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declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
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