Craig Topper ba1d901967 [RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200) ...

The input is an integer which can't be NAN so the NV(invalid) exception
can't be raised. The conversion is exact so it can't raise NX(inexact),
UF(underflow), or OF(overflow). The instructions are not divide so they
can't raise DZ(divide by zero).

Fixes #133192.

2025-03-27 07:45:42 -07:00

..

rvv

[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)

2025-02-12 12:06:55 +08:00

alu_m-rv32.mir

…

alu_m-rv64.mir

[RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.

2024-11-11 15:08:50 -08:00

alu-rv32.mir

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427)

2024-12-10 22:17:52 -08:00

alu-rv64.mir

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559)

2024-11-11 20:59:21 -08:00

brcond-rv32.mir

…

brcond-rv64.mir

…

brindirect-rv32.mir

…

brindirect-rv64.mir

…

bswap-rv32.mir

…

bswap-rv64.mir

…

constant32.mir

…

constant64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

copy32.mir

…

copy64.mir

…

ctlz-rv32.mir

…

ctlz-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

ctpop-rv32.mir

…

ctpop-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

cttz-rv32.mir

…

cttz-rv64.mir

[RISCV][GISel] Remove s32 support for G_CTPOP/CTLZ/CTTZ on RV64. (#115101)

2024-11-07 10:40:14 -08:00

fcmp-f16-rv32.mir

…

fcmp-f16-rv64.mir

…

fcmp-rv32.mir

…

fcmp-rv64.mir

…

fp-arith-f16.mir

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)

2024-11-07 17:07:31 -08:00

fp-arith.mir

[RISCV][GISel] Add fcopysign tests with mismatched types. NFC (#115364)

2024-11-07 17:07:31 -08:00

fp-constant-f16.mir

…

fp-constant.mir

…

fp-ext-trunc-f16.mir

…

fp-ext-trunc.mir

…

fp-load-store.mir

[RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.

2024-11-17 11:39:59 -08:00

fp-select-rv32.mir

…

fp-select-rv64.mir

…

fptoi-f16-rv32.mir

…

fptoi-f16-rv64.mir

[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)

2024-11-07 17:08:58 -08:00

fptoi-rv32.mir

…

fptoi-rv64.mir

[RISCV][GISel] Custom promote s32 G_FPTOSI/FPTOUI on RV64. (#115268)

2024-11-07 17:08:58 -08:00

frame-index-rv32.mir

…

frame-index-rv64.mir

…

global-value32.mir

…

global-value64.mir

…

icmp-rv32.mir

…

icmp-rv64.mir

…

implicit-def-rv32.mir

…

implicit-def-rv64.mir

…

int-ptr-cast-rv32.mir

…

int-ptr-cast-rv64.mir

…

is-fpclass-f16-rv32.mir

…

is-fpclass-f16-rv64.mir

…

is-fpclass-rv32.mir

…

is-fpclass-rv64.mir

…

itofp-f16-rv32.mir

…

itofp-f16-rv64.mir

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

2024-11-07 13:57:11 -08:00

itofp-rv32.mir

[RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (#133200)

2025-03-27 07:45:42 -07:00

itofp-rv64.mir

[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)

2024-11-07 13:57:11 -08:00

load-rv32.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

load-rv64.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

merge-unmerge-rv32.mir

…

minmax-rv32.mir

…

minmax-rv64.mir

…

phi-rv32.mir

…

phi-rv64.mir

…

ptradd-rv32.mir

…

ptradd-rv64.mir

…

ptrmask-rv32.mir

…

ptrmask-rv64.mir

…

rotate-rv32.mir

…

rotate-rv64.mir

[RISCV][GISel] Custom promote s32 G_ROTL/ROTR on RV64. (#115107)

2024-11-07 13:24:22 -08:00

select-rv32.mir

…

select-rv64.mir

…

sext-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

shift-rv32.mir

…

shift-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00

store-rv32.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

store-rv64.mir

[RISCV][GISel] Make extended loads and truncating stores with s16 register type and s8 memory type legal.

2024-11-19 11:57:35 -08:00

trap.mir

…

zba-rv32.mir

…

zba-rv64.mir

[RISCV][GISel] Remove most patterns that look for a zext i32->i64 and another integer instruction.

2024-11-14 14:03:02 -08:00

zext-rv64.mir

[RISCV][GISel] Promote s32 G_CONSTANT on RV64.

2024-11-11 23:35:02 -08:00