bc91f3cdd5
This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to only spill 32 bits.
I've added CodeGenOnly instructions for load/store using GPRF32 as that gave better results than insert_subreg/extract_subreg.
Function arguments use this new GPRF32 register class for f32 arguments with Zfinx. Eliminating the need to use RISCVISD::FMV* nodes.
This is similar to #107446 which adds a 16 bit register class.
78 lines
2.4 KiB
LLVM
78 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32f | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64f | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32 | FileCheck --check-prefixes=CHECKZFINX,RV32ZFINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64 | FileCheck --check-prefixes=CHECKZFINX,RV64ZFINX %s
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; TODO: constant pool shouldn't be necessary for RV64IF.
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define float @float_imm() nounwind {
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; CHECK-LABEL: float_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
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; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
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; CHECK-NEXT: ret
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;
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; RV32ZFINX-LABEL: float_imm:
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; RV32ZFINX: # %bb.0:
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; RV32ZFINX-NEXT: lui a0, 263313
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; RV32ZFINX-NEXT: addi a0, a0, -37
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; RV32ZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
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; RV32ZFINX-NEXT: ret
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;
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; RV64ZFINX-LABEL: float_imm:
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; RV64ZFINX: # %bb.0:
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; RV64ZFINX-NEXT: lui a0, 263313
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; RV64ZFINX-NEXT: addiw a0, a0, -37
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; RV64ZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
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; RV64ZFINX-NEXT: ret
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ret float 3.14159274101257324218750
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}
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define float @float_imm_op(float %a) nounwind {
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; CHECK-LABEL: float_imm_op:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 260096
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fadd.s fa0, fa0, fa5
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; CHECK-NEXT: ret
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;
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; CHECKZFINX-LABEL: float_imm_op:
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; CHECKZFINX: # %bb.0:
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; CHECKZFINX-NEXT: lui a1, 260096
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; CHECKZFINX-NEXT: fadd.s a0, a0, a1
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; CHECKZFINX-NEXT: ret
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%1 = fadd float %a, 1.0
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ret float %1
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}
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define float @float_positive_zero(ptr %pf) nounwind {
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; CHECK-LABEL: float_positive_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.w.x fa0, zero
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; CHECK-NEXT: ret
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;
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; CHECKZFINX-LABEL: float_positive_zero:
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; CHECKZFINX: # %bb.0:
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; CHECKZFINX-NEXT: li a0, 0
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; CHECKZFINX-NEXT: ret
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ret float 0.0
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}
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define float @float_negative_zero(ptr %pf) nounwind {
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; CHECK-LABEL: float_negative_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 524288
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; CHECK-NEXT: fmv.w.x fa0, a0
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; CHECK-NEXT: ret
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;
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; CHECKZFINX-LABEL: float_negative_zero:
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; CHECKZFINX: # %bb.0:
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; CHECKZFINX-NEXT: lui a0, 524288
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; CHECKZFINX-NEXT: ret
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ret float -0.0
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}
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