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clang-p2996/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
Philip Reames 2175c6cb38 [RISCV] Set AllocationPriority in line with LMUL (#131176) 
This mechanism causes the greedy register allocator to prefer allocating
register classes with higher priority first. This helps to ensure that
high LMUL registers obtain a register without having to go through the
eviction mechanism. In practice, it seems to cause a bunch of code
churn, and some minor improvement around widening and narrowing
operations.

In a few of the widening tests, we have what look like code size
regressions because we end up with two smaller register class copies
instead of one larger one after the instruction. However, in any larger
code sequence, these are likely to be folded into the producing
instructions. (But so were the wider copies after the operation.)

Two observations:
1) We're not setting the greedy-regclass-priority-trumps-globalness flag
   on the register class, so this doesn't help long mask ranges.  I
   thought about doing that, but the benefit is non-obvious, so I
   decided it was worth a separate change at minimum.
2) We could arguably set the priority higher for the register classes
   that exclude v0.  I tried that, and it caused a whole bunch of
   further churn.  I may return to it in a separate patch.
2025-03-18 08:25:49 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB
; Integers
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v12, v8, v10
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vwmaccu.vx v12, a1, v10
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v32i1_v16i1:
; ZVBB: # %bb.0:
; ZVBB-NEXT: li a0, 32
; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVBB-NEXT: vslideup.vi v0, v8, 2
; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; ZVBB-NEXT: vmv.v.i v8, 0
; ZVBB-NEXT: vmerge.vim v8, v8, 1, v0
; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; ZVBB-NEXT: vslidedown.vi v10, v8, 16
; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVBB-NEXT: vwsll.vi v12, v10, 8
; ZVBB-NEXT: vwaddu.wv v12, v12, v8
; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
}
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vwaddu.vv v8, v11, v10
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16i16_v8i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vmv1r.v v11, v8
; ZVBB-NEXT: vwsll.vi v8, v10, 16
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
ret <16 x i16> %res
}
define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: vector_interleave_v8i32_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vwaddu.vv v8, v11, v10
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8i32_v4i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vmv1r.v v11, v8
; ZVBB-NEXT: li a0, 32
; ZVBB-NEXT: vwsll.vx v8, v10, a0
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
}
define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vector_interleave_v4i64_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: lui a0, 12304
; CHECK-NEXT: addi a0, a0, 512
; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4i64_v2i64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: lui a0, 12304
; ZVBB-NEXT: addi a0, a0, 512
; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: vmv.s.x v10, a0
; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vsext.vf2 v12, v10
; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
}
define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {
; CHECK-LABEL: vector_interleave3_v6i32_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: vle32.v v9, (a2)
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vle32.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave3_v6i32_v2i32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: vle32.v v9, (a2)
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: add a1, a2, a1
; ZVBB-NEXT: vle32.v v10, (a1)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
}
define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) {
; CHECK-LABEL: vector_interleave5_v10i16_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: add a4, a3, a1
; CHECK-NEXT: vle16.v v9, (a2)
; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: vle16.v v12, (a3)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: add a1, a4, a1
; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v12, v11, 2
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave5_v10i16_v2i16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: add a4, a3, a1
; ZVBB-NEXT: vle16.v v9, (a2)
; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: vle16.v v12, (a3)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: add a1, a4, a1
; ZVBB-NEXT: vle16.v v10, (a1)
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v12, v11, 2
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 4
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
}
define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g) {
; CHECK-LABEL: vector_interleave7_v14i8_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: add a4, a3, a1
; CHECK-NEXT: vsetvli a5, zero, e8, mf8, ta, ma
; CHECK-NEXT: vsseg7e8.v v8, (a0)
; CHECK-NEXT: vle8.v v9, (a4)
; CHECK-NEXT: add a4, a4, a1
; CHECK-NEXT: vle8.v v10, (a2)
; CHECK-NEXT: add a2, a4, a1
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vle8.v v11, (a2)
; CHECK-NEXT: vle8.v v12, (a4)
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v13, (a1)
; CHECK-NEXT: vle8.v v14, (a3)
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v11, 2
; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v13, 4
; CHECK-NEXT: vslideup.vi v8, v14, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 6
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave7_v14i8_v2i8:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 3
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
; ZVBB-NEXT: add a4, a3, a1
; ZVBB-NEXT: vsetvli a5, zero, e8, mf8, ta, ma
; ZVBB-NEXT: vsseg7e8.v v8, (a0)
; ZVBB-NEXT: vle8.v v9, (a4)
; ZVBB-NEXT: add a4, a4, a1
; ZVBB-NEXT: vle8.v v10, (a2)
; ZVBB-NEXT: add a2, a4, a1
; ZVBB-NEXT: add a1, a2, a1
; ZVBB-NEXT: vle8.v v11, (a2)
; ZVBB-NEXT: vle8.v v12, (a4)
; ZVBB-NEXT: vle8.v v8, (a0)
; ZVBB-NEXT: vle8.v v13, (a1)
; ZVBB-NEXT: vle8.v v14, (a3)
; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; ZVBB-NEXT: vslideup.vi v12, v11, 2
; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; ZVBB-NEXT: vslideup.vi v12, v13, 4
; ZVBB-NEXT: vslideup.vi v8, v14, 4
; ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 6
; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 8
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <14 x i8> @llvm.vector.interleave7.v14i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g)
ret <14 x i8> %res
}
; Floats
define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vector_interleave_v4f16_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f16_v2f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
ret <4 x half> %res
}
define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vector_interleave_v8f16_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f16_v4f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vwsll.vi v10, v9, 16
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
}
define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vector_interleave_v4f32_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v10, a0, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f32_v2f32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: li a0, 32
; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vwsll.vx v10, v9, a0
; ZVBB-NEXT: vwaddu.wv v10, v10, v8
; ZVBB-NEXT: vmv1r.v v8, v10
; ZVBB-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
}
define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: vector_interleave_v16f16_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vwaddu.vv v8, v11, v10
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v16f16_v8f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vmv1r.v v11, v8
; ZVBB-NEXT: vwsll.vi v8, v10, 16
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
}
define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: vector_interleave_v8f32_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmv1r.v v11, v8
; CHECK-NEXT: vwaddu.vv v8, v11, v10
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vwmaccu.vx v8, a0, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v8f32_v4f32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: vmv1r.v v11, v8
; ZVBB-NEXT: li a0, 32
; ZVBB-NEXT: vwsll.vx v8, v10, a0
; ZVBB-NEXT: vwaddu.wv v8, v8, v11
; ZVBB-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
}
define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: vector_interleave_v4f64_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: lui a0, 12304
; CHECK-NEXT: addi a0, a0, 512
; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vsext.vf2 v12, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_v4f64_v2f64:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v9
; ZVBB-NEXT: lui a0, 12304
; ZVBB-NEXT: addi a0, a0, 512
; ZVBB-NEXT: vslideup.vi v8, v10, 2
; ZVBB-NEXT: vmv.s.x v10, a0
; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVBB-NEXT: vsext.vf2 v12, v10
; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12
; ZVBB-NEXT: vmv.v.v v8, v10
; ZVBB-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
}
define <6 x float> @vector_interleave3_v632_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; CHECK-LABEL: vector_interleave3_v632_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsseg3e32.v v8, (a0)
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: vle32.v v9, (a2)
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vle32.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave3_v632_v2f32:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 1
; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: vle32.v v9, (a2)
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: add a1, a2, a1
; ZVBB-NEXT: vle32.v v10, (a1)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <6 x float> @llvm.vector.interleave3.v6f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <6 x float> %res
}
define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e) {
; CHECK-LABEL: vector_interleave5_v10f16_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
; CHECK-NEXT: add a4, a3, a1
; CHECK-NEXT: vle16.v v9, (a2)
; CHECK-NEXT: vle16.v v11, (a4)
; CHECK-NEXT: vle16.v v12, (a3)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: add a1, a4, a1
; CHECK-NEXT: vle16.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v12, v11, 2
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave5_v10f16_v2f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
; ZVBB-NEXT: add a4, a3, a1
; ZVBB-NEXT: vle16.v v9, (a2)
; ZVBB-NEXT: vle16.v v11, (a4)
; ZVBB-NEXT: vle16.v v12, (a3)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: add a1, a4, a1
; ZVBB-NEXT: vle16.v v10, (a1)
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v12, v11, 2
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 4
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 8
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <10 x half> @llvm.vector.interleave5.v10f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e)
ret <10 x half> %res
}
define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g) {
; CHECK-LABEL: vector_interleave7_v7f16_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a2, a0, a1
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: add a4, a3, a1
; CHECK-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
; CHECK-NEXT: vsseg7e16.v v8, (a0)
; CHECK-NEXT: vle16.v v9, (a4)
; CHECK-NEXT: add a4, a4, a1
; CHECK-NEXT: vle16.v v10, (a2)
; CHECK-NEXT: add a2, a4, a1
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: vle16.v v11, (a2)
; CHECK-NEXT: vle16.v v12, (a4)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v13, (a1)
; CHECK-NEXT: vle16.v v14, (a3)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v11, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v12, v13, 2
; CHECK-NEXT: vslideup.vi v8, v14, 2
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave7_v7f16_v1f16:
; ZVBB: # %bb.0:
; ZVBB-NEXT: addi sp, sp, -16
; ZVBB-NEXT: .cfi_def_cfa_offset 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: srli a1, a1, 2
; ZVBB-NEXT: add a2, a0, a1
; ZVBB-NEXT: add a3, a2, a1
; ZVBB-NEXT: add a4, a3, a1
; ZVBB-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg7e16.v v8, (a0)
; ZVBB-NEXT: vle16.v v9, (a4)
; ZVBB-NEXT: add a4, a4, a1
; ZVBB-NEXT: vle16.v v10, (a2)
; ZVBB-NEXT: add a2, a4, a1
; ZVBB-NEXT: add a1, a2, a1
; ZVBB-NEXT: vle16.v v11, (a2)
; ZVBB-NEXT: vle16.v v12, (a4)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vle16.v v13, (a1)
; ZVBB-NEXT: vle16.v v14, (a3)
; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
; ZVBB-NEXT: vslideup.vi v12, v11, 1
; ZVBB-NEXT: vslideup.vi v8, v10, 1
; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
; ZVBB-NEXT: vslideup.vi v12, v13, 2
; ZVBB-NEXT: vslideup.vi v8, v14, 2
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 3
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v12, 4
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a0, a0, 1
; ZVBB-NEXT: add sp, sp, a0
; ZVBB-NEXT: .cfi_def_cfa sp, 16
; ZVBB-NEXT: addi sp, sp, 16
; ZVBB-NEXT: .cfi_def_cfa_offset 0
; ZVBB-NEXT: ret
%res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
ret <7 x half> %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
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