2175c6cb38
This mechanism causes the greedy register allocator to prefer allocating register classes with higher priority first. This helps to ensure that high LMUL registers obtain a register without having to go through the eviction mechanism. In practice, it seems to cause a bunch of code churn, and some minor improvement around widening and narrowing operations. In a few of the widening tests, we have what look like code size regressions because we end up with two smaller register class copies instead of one larger one after the instruction. However, in any larger code sequence, these are likely to be folded into the producing instructions. (But so were the wider copies after the operation.) Two observations: 1) We're not setting the greedy-regclass-priority-trumps-globalness flag on the register class, so this doesn't help long mask ranges. I thought about doing that, but the benefit is non-obvious, so I decided it was worth a separate change at minimum. 2) We could arguably set the priority higher for the register classes that exclude v0. I tried that, and it caused a whole bunch of further churn. I may return to it in a separate patch.
889 lines
34 KiB
LLVM
889 lines
34 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV32ZVBB
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV64ZVBB
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; ==============================================================================
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; i32 -> i64
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; ==============================================================================
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define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: vwsll_vv_nxv2i64_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
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; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
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; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vv_nxv2i64_zext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: vwsll_vv_nxv2i64_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
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; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
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; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64(<vscale x 2 x i32> %a, i64 %b) {
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; CHECK-LABEL: vwsll_vx_i64_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsll.vx v8, v10, a0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
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%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %splat
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_sext(<vscale x 2 x i32> %a, i32 %b) {
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; CHECK-LABEL: vwsll_vx_i32_nxv2i64_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsext.vf2 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
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%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_zext(<vscale x 2 x i32> %a, i32 %b) {
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; CHECK-LABEL: vwsll_vx_i32_nxv2i64_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf2 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
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%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_sext(<vscale x 2 x i32> %a, i16 %b) {
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; CHECK-LABEL: vwsll_vx_i16_nxv2i64_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsext.vf4 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
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%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_zext(<vscale x 2 x i32> %a, i16 %b) {
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; CHECK-LABEL: vwsll_vx_i16_nxv2i64_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf4 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
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%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_sext(<vscale x 2 x i32> %a, i8 %b) {
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; CHECK-LABEL: vwsll_vx_i8_nxv2i64_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsext.vf8 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
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%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {
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; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf8 v8, v12
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; CHECK-NEXT: vsll.vv v8, v10, v8
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
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%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a) {
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; CHECK-LABEL: vwsll_vi_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: li a0, 4
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; CHECK-NEXT: vwmulu.vx v8, v10, a0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, splat (i64 2)
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ret <vscale x 2 x i64> %z
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}
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; ==============================================================================
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; i16 -> i32
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; ==============================================================================
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define <vscale x 4 x i32> @vwsll_vv_nxv4i32_sext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
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; CHECK-LABEL: vwsll_vv_nxv4i32_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
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; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
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; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
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%y = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>
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%z = shl <vscale x 4 x i32> %x, %y
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ret <vscale x 4 x i32> %z
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}
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define <vscale x 4 x i32> @vwsll_vv_nxv4i32_zext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
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; CHECK-LABEL: vwsll_vv_nxv4i32_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
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; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
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; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
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%y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
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%z = shl <vscale x 4 x i32> %x, %y
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ret <vscale x 4 x i32> %z
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}
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define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {
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; CHECK-LABEL: vwsll_vx_i64_nxv4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsll.vx v8, v10, a0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
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; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %y
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vx_i32_nxv4i32(<vscale x 4 x i16> %a, i32 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i32_nxv4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv4i32:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %splat
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_sext(<vscale x 4 x i16> %a, i16 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i16_nxv4i32_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%y = sext <vscale x 4 x i16> %splat to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %y
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_zext(<vscale x 4 x i16> %a, i16 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i16_nxv4i32_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vzext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%y = zext <vscale x 4 x i16> %splat to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %y
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_sext(<vscale x 4 x i16> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv4i32_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsext.vf4 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%y = sext <vscale x 4 x i8> %splat to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %y
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_zext(<vscale x 4 x i16> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv4i32_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vzext.vf4 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%y = zext <vscale x 4 x i8> %splat to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, %y
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
define <vscale x 4 x i32> @vwsll_vi_nxv4i32(<vscale x 4 x i16> %a) {
|
|
; CHECK-LABEL: vwsll_vi_nxv4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v10, v8
|
|
; CHECK-NEXT: li a0, 4
|
|
; CHECK-NEXT: vwmulu.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vi_nxv4i32:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
|
|
%z = shl <vscale x 4 x i32> %x, splat (i32 2)
|
|
ret <vscale x 4 x i32> %z
|
|
}
|
|
|
|
; ==============================================================================
|
|
; i8 -> i16
|
|
; ==============================================================================
|
|
|
|
define <vscale x 8 x i16> @vwsll_vv_nxv8i16_sext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
|
|
; CHECK-LABEL: vwsll_vv_nxv8i16_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsext.vf2 v12, v9
|
|
; CHECK-NEXT: vsll.vv v8, v10, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vv_nxv8i16_zext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
|
|
; CHECK-LABEL: vwsll_vv_nxv8i16_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vzext.vf2 v12, v9
|
|
; CHECK-NEXT: vsll.vv v8, v10, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v9
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v11, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i64_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
|
|
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i32_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
|
|
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = trunc <vscale x 8 x i32> %splat to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vx_i16_nxv8i16(<vscale x 8 x i8> %a, i16 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i16_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv8i16:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
|
|
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %splat
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_sext(<vscale x 8 x i8> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv8i16_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vsext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = sext <vscale x 8 x i8> %splat to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_zext(<vscale x 8 x i8> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv8i16_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf2 v10, v8
|
|
; CHECK-NEXT: vzext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%y = zext <vscale x 8 x i8> %splat to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, %y
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) {
|
|
; CHECK-LABEL: vwsll_vi_nxv8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmv1r.v v10, v8
|
|
; CHECK-NEXT: li a0, 4
|
|
; CHECK-NEXT: vwmulu.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vi_nxv8i16:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv1r.v v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
|
|
%z = shl <vscale x 8 x i16> %x, splat (i16 2)
|
|
ret <vscale x 8 x i16> %z
|
|
}
|
|
|
|
; ==============================================================================
|
|
; i8 -> i64
|
|
; ==============================================================================
|
|
|
|
define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
|
|
; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsext.vf8 v12, v9
|
|
; CHECK-NEXT: vsll.vv v8, v10, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9
|
|
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
|
|
; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vzext.vf8 v12, v9
|
|
; CHECK-NEXT: vsll.vv v8, v10, v12
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9
|
|
; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %splat
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
|
|
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-ZVBB-NEXT: vsext.vf2 v8, v12
|
|
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vzext.vf2 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsext.vf4 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
|
|
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-ZVBB-NEXT: vsext.vf4 v8, v12
|
|
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vzext.vf4 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsext.vf8 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
|
|
; CHECK-ZVBB-NEXT: vmv.v.x v12, a0
|
|
; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-ZVBB-NEXT: vsext.vf8 v8, v12
|
|
; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) {
|
|
; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vmv.v.x v12, a0
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vzext.vf8 v8, v12
|
|
; CHECK-NEXT: vsll.vv v8, v10, v8
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
|
|
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, %y
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
|
|
define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {
|
|
; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vzext.vf8 v10, v8
|
|
; CHECK-NEXT: vsll.vi v8, v10, 2
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
|
|
; CHECK-ZVBB: # %bb.0:
|
|
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
|
|
; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
|
|
; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
|
|
; CHECK-ZVBB-NEXT: ret
|
|
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
|
|
%z = shl <vscale x 2 x i64> %x, splat (i64 2)
|
|
ret <vscale x 2 x i64> %z
|
|
}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; RV32ZVBB: {{.*}}
|
|
; RV64ZVBB: {{.*}}
|