Files
clang-p2996/llvm/test/CodeGen/RISCV/split-sp-adjust.ll
Fangrui Song eabaee0c59 [RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.
2024-01-07 12:09:44 -08:00

44 lines
1.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; The stack size is 2048 and the SP adjustment will be split.
define i32 @SplitSP() nounwind {
; RV32I-LABEL: SplitSP:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: addi a0, sp, 16
; RV32I-NEXT: call foo
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret
entry:
%xx = alloca [2028 x i8], align 1
%call = call i32 @foo(ptr nonnull %xx)
ret i32 0
}
; The stack size is 2032 and the SP adjustment will not be split.
define i32 @NoSplitSP() nounwind {
; RV32I-LABEL: NoSplitSP:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -2032
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a0, sp, 4
; RV32I-NEXT: call foo
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 2032
; RV32I-NEXT: ret
entry:
%xx = alloca [2024 x i8], align 1
%call = call i32 @foo(ptr nonnull %xx)
ret i32 0
}
declare i32 @foo(ptr)