8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
77 lines
1.9 KiB
LLVM
77 lines
1.9 KiB
LLVM
; Test vector division on arch15.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
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; Test a v4i32 signed division.
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define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vdf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = sdiv <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v4i32 unsigned division.
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define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vdlf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = udiv <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v4i32 signed remainder.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vrf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = srem <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v4i32 unsigned remainder.
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define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vrlf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = urem <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v2i64 signed division.
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define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vdg %v24, %v26, %v28
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; CHECK: br %r14
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%ret = sdiv <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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; Test a v2i64 unsigned division.
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define <2 x i64> @f6(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vdlg %v24, %v26, %v28
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; CHECK: br %r14
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%ret = udiv <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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; Test a v2i64 signed remainder.
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define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f7:
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; CHECK: vrg %v24, %v26, %v28
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; CHECK: br %r14
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%ret = srem <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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; Test a v2i64 unsigned remainder.
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define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vrlg %v24, %v26, %v28
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; CHECK: br %r14
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%ret = urem <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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