a33a84ee63
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test gfx940 and gfx941 are no longer supported. This is one of a series of PRs to remove them from the code base. This PR uses gfx942 instead of gfx940 and gfx941 in the test RUN-lines (unless there is already a RUN-line for gfx942). The only notable difference in the test output is that gfx942 does not force the use of sc0 and sc1 on stores while gfx940 and gfx941 do (cf. https://reviews.llvm.org/D149986). For SWDEV-512631
21 lines
918 B
LLVM
21 lines
918 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -mtriple=amdgcn-amd-amdhsa --mcpu=gfx942 -passes=load-store-vectorizer -S -o - %s | FileCheck %s
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; Don't crash when checking for misaligned accesses with sub-byte size.
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define void @misaligned_access_i1(ptr addrspace(3) %in) #0 {
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; CHECK-LABEL: define void @misaligned_access_i1(
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; CHECK-SAME: ptr addrspace(3) [[IN:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[IN_GEP_1:%.*]] = getelementptr i1, ptr addrspace(3) [[IN]], i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i1>, ptr addrspace(3) [[IN_GEP_1]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i1>, ptr addrspace(3) [[IN]], align 1
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; CHECK-NEXT: ret void
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;
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%in.gep.1 = getelementptr i1, ptr addrspace(3) %in, i32 1
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%1 = load <16 x i1>, ptr addrspace(3) %in.gep.1, align 4
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%2 = load <8 x i1>, ptr addrspace(3) %in, align 1
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ret void
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}
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