c482b8faea
Instead of executing the whole entry VPIRBB twice, first only execute the VPExpandSCEVRecipes and replace their uses with the expanded VPValue, which will be a live-in. This allows removing special logic in VPExpandSCEVRecipe to support executing twice and allows moving the ExpandedSCEVs map out of VPTransformState. It will also allow adding other recipes to the entry VPBB in the future.
103 lines
5.2 KiB
LLVM
103 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 | FileCheck %s
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; Check that we can vectorize this loop without crashing.
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define i8 @widget(ptr %arr, i8 %t9) {
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; CHECK-LABEL: @widget(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[ARR1:%.*]] = ptrtoint ptr [[ARR:%.*]] to i64
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; CHECK-NEXT: br label [[BB6:%.*]]
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; CHECK: bb6:
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; CHECK-NEXT: [[T1_0:%.*]] = phi ptr [ [[ARR]], [[BB:%.*]] ], [ null, [[BB6]] ]
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; CHECK-NEXT: [[C:%.*]] = call i1 @cond()
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; CHECK-NEXT: br i1 [[C]], label [[FOR_PREHEADER:%.*]], label [[BB6]]
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; CHECK: for.preheader:
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; CHECK-NEXT: [[T1_0_LCSSA:%.*]] = phi ptr [ [[T1_0]], [[BB6]] ]
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; CHECK-NEXT: [[T1_0_LCSSA4:%.*]] = phi ptr [ [[T1_0]], [[BB6]] ]
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; CHECK-NEXT: [[T1_0_LCSSA1:%.*]] = phi ptr [ [[T1_0]], [[BB6]] ]
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; CHECK-NEXT: [[T1_0_LCSSA3:%.*]] = ptrtoint ptr [[T1_0_LCSSA]] to i64
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; CHECK-NEXT: [[T1_0_LCSSA2:%.*]] = ptrtoint ptr [[T1_0_LCSSA4]] to i64
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; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[ARR1]] to i32
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; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[T1_0_LCSSA3]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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; CHECK: vector.scevcheck:
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; CHECK-NEXT: [[TMP4:%.*]] = sub i64 -1, [[ARR1]]
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], [[T1_0_LCSSA2]]
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i8
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; CHECK-NEXT: [[TMP7:%.*]] = add i8 1, [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = icmp slt i8 [[TMP7]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP5]], 255
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; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP8]], [[TMP9]]
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; CHECK-NEXT: br i1 [[TMP10]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP3]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP3]], [[N_MOD_VF]]
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; CHECK-NEXT: [[IND_END:%.*]] = trunc i32 [[N_VEC]] to i8
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[T9:%.*]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ <i8 0, i8 1, i8 2, i8 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 1)
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; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i8> [[TMP11]], i32 0
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[ARR]], i8 [[TMP12]]
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; CHECK-NEXT: [[TMP14:%.*]] = icmp slt <4 x i8> [[TMP11]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP15:%.*]] = zext <4 x i1> [[TMP14]] to <4 x i8>
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[TMP13]], i32 0
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; CHECK-NEXT: store <4 x i8> [[TMP15]], ptr [[TMP16]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4)
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP3]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i8, ptr [[ARR]], i8 [[IV_NEXT]]
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; CHECK-NEXT: [[T3_I:%.*]] = icmp slt i8 [[IV_NEXT]], [[T9]]
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; CHECK-NEXT: [[T3_I8:%.*]] = zext i1 [[T3_I]] to i8
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; CHECK-NEXT: store i8 [[T3_I8]], ptr [[PTR]], align 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[T1_0_LCSSA1]], [[PTR]]
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; CHECK-NEXT: br i1 [[EC]], label [[FOR_EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: for.exit:
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i8 [ [[IV_NEXT]], [[FOR_BODY]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i8 [[IV_NEXT_LCSSA]]
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;
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bb:
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br label %bb6
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bb6:
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%t1.0 = phi ptr [ %arr, %bb ], [ null, %bb6 ]
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%c = call i1 @cond()
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br i1 %c, label %for.preheader, label %bb6
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for.preheader:
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br label %for.body
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for.body:
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%iv = phi i8 [ %iv.next, %for.body ], [ 0, %for.preheader ]
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%iv.next = add i8 %iv, 1
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%ptr = getelementptr inbounds i8, ptr %arr, i8 %iv.next
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%t3.i = icmp slt i8 %iv.next, %t9
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%t3.i8 = zext i1 %t3.i to i8
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store i8 %t3.i8, ptr %ptr
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%ec = icmp eq ptr %t1.0, %ptr
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br i1 %ec, label %for.exit, label %for.body
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for.exit:
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%iv.next.lcssa = phi i8 [ %iv.next, %for.body ]
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ret i8 %iv.next.lcssa
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}
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declare i1 @cond()
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