58a94b1d0a
Need to look through the SExt/ZExt scalars to be gathered, when trying to reduce their width after minbitwidth analysis to prevent permanent attempts to revectorize such gathered instructions.
40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=systemz -mcpu=z15 %s | FileCheck %s
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define void @test(ptr %a, i8 %0, i16 %b.promoted.i) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: ptr [[A:%.*]], i8 [[TMP0:%.*]], i16 [[B_PROMOTED_I:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i16
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; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]])
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; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP9]] to i64
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; CHECK-NEXT: [[OP_RDX:%.*]] = and i64 [[TMP11]], 1
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; CHECK-NEXT: store i64 [[OP_RDX]], ptr [[A]], align 8
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; CHECK-NEXT: ret void
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;
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%2 = zext i8 %0 to i128
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%3 = zext i16 %b.promoted.i to i128
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%4 = or i128 %3, %2
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%5 = trunc i128 %4 to i64
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%6 = and i64 %5, 1
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%7 = zext i16 %b.promoted.i to i128
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%8 = or i128 %7, %2
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%9 = trunc i128 %8 to i64
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%10 = and i64 %6, %9
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%11 = zext i16 %b.promoted.i to i128
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%12 = or i128 %11, %2
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%13 = trunc i128 %12 to i64
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%14 = and i64 %10, %13
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%15 = zext i16 %b.promoted.i to i128
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%16 = or i128 %15, %2
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%17 = trunc i128 %16 to i64
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%18 = and i64 %14, %17
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store i64 %18, ptr %a, align 8
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ret void
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}
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