Min-Yih Hsu aa207c3f05 [RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165) ...

P500-series cores should have a floating point load latency closer to 5
cycles, just like P400- and P600-series cores.

2025-03-27 11:00:07 -07:00

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AArch64

[MCA] Extend -instruction-tables option with verbosity levels (#130574)

2025-03-25 09:19:57 -07:00

AMDGPU

[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)

2025-02-13 15:17:12 +01:00

ARM

[ARM] Reject fixed-point VCVT with different registers (#126232)

2025-02-07 14:32:15 +00:00

JSON/X86

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RISCV

[RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165)

2025-03-27 11:00:07 -07:00

SystemZ

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X86

[X86] Handle BSF/BSR "zero-input pass through" behaviour (#123623)

2025-01-23 12:59:59 +00:00

invalid_input_file_name.test

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lit.local.cfg

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