f4bb9b53ad
Option becomes: -instruction-tables=`<level>` The choice of `<level>` controls number of printed information. `<level>` may be `none` (default), `normal`, `full`. Note: If the option is used without `<label>`, default is `normal` (legacy). When `<level>` is `full`, additional information are: - `<Bypass Latency>`: Latency when a bypass is implemented between operands in pipelines (see SchedReadAdvance). - `<LLVM Opcode Name>`: mnemonic plus operands identifier. - `<Resources units>`: Used resources associated with LLVM Opcode. - `<instruction comment>`: reports comment if any from source assembly. Level `full` can be used to better check scheduling info when TableGen is modified. LLVM Opcode name help to find right instruction regexp to fix TableGen Scheduling Info. -instruction-tables=full option is validated on AArch64/Neoverse/V1-sve-instructions.s Follow up of MR #126703 --------- Co-authored-by: Julien Villette <julien.villette@sipearl.com>
286 lines
10 KiB
C++
286 lines
10 KiB
C++
//===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the InstructionInfoView API.
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///
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//===----------------------------------------------------------------------===//
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#include "Views/InstructionInfoView.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/JSON.h"
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#include "llvm/Support/WithColor.h"
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namespace llvm {
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namespace mca {
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void InstructionInfoView::getComment(raw_ostream &OS, const MCInst &MCI) const {
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StringRef S = MCI.getLoc().getPointer();
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size_t Pos = 0, PosCmt = 0;
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// Recognized comments are after assembly instructions on the same line.
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// It is usefull to add in comment scheduling information from architecture
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// specification.
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// '#' comment mark is not supported by llvm-mca
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if (Pos = S.find("\n"); Pos != StringRef::npos) {
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StringRef InstrStr = S.take_front(Pos);
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// C style comment
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if (((PosCmt = InstrStr.find("/*")) != StringRef::npos) &&
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((Pos = InstrStr.find("*/")) != StringRef::npos)) {
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OS << InstrStr.substr(PosCmt, Pos);
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return;
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}
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// C++ style comment
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if ((PosCmt = InstrStr.find("//")) != StringRef::npos) {
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OS << InstrStr.substr(PosCmt);
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}
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}
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}
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void InstructionInfoView::printView(raw_ostream &OS) const {
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std::string Buffer;
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raw_string_ostream TempStream(Buffer);
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formatted_raw_ostream FOS(TempStream);
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ArrayRef<llvm::MCInst> Source = getSource();
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if (!Source.size())
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return;
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IIVDVec IIVD(Source.size());
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collectData(IIVD);
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if (PrintFullInfo) {
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FOS << "\n\nResources:\n";
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const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
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for (unsigned I = 1, ResourceIndex = 0, E = SM.getNumProcResourceKinds();
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I < E; ++I) {
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const MCProcResourceDesc &ProcResource = *SM.getProcResource(I);
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unsigned NumUnits = ProcResource.NumUnits;
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// Skip invalid resources with zero units.
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if (!NumUnits)
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continue;
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FOS << '[' << ResourceIndex << ']';
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FOS.PadToColumn(6);
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FOS << "- " << ProcResource.Name << ':' << NumUnits;
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if (ProcResource.SubUnitsIdxBegin) {
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FOS.PadToColumn(20);
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for (unsigned U = 0; U < NumUnits; ++U) {
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FOS << SM.getProcResource(ProcResource.SubUnitsIdxBegin[U])->Name;
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if ((U + 1) < NumUnits)
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FOS << ", ";
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}
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}
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FOS << '\n';
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ResourceIndex++;
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}
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}
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SmallVector<unsigned, 16> Paddings = {0, 7, 14, 21, 28, 35, 42};
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SmallVector<StringRef, 16> Fields = {"#uOps", "Latency",
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"RThroughput", "MayLoad",
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"MayStore", "HasSideEffects (U)"};
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SmallVector<StringRef, 8> EndFields;
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unsigned LastPadding = Paddings.back();
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if (PrintFullInfo) {
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Fields.push_back("Bypass Latency");
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// Reserving 7 chars for
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Paddings.push_back(LastPadding += 7);
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Fields.push_back("Resources (<Name> | <Name>[<ReleaseAtCycle>] | "
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"<Name>[<AcquireAtCycle>,<ReleaseAtCycle])");
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Paddings.push_back(LastPadding += 43);
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Fields.push_back("LLVM Opcode Name");
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Paddings.push_back(LastPadding += 27);
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}
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if (PrintBarriers) {
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Fields.push_back("LoadBarrier");
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Paddings.push_back(LastPadding += 7);
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Fields.push_back("StoreBarrier");
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Paddings.push_back(LastPadding += 7);
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}
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if (PrintEncodings) {
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Fields.push_back("Encoding Size");
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Paddings.push_back(LastPadding += 7);
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EndFields.push_back("Encodings:");
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Paddings.push_back(LastPadding += 30);
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}
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EndFields.push_back("Instructions:");
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FOS << "\n\nInstruction Info:\n";
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for (unsigned i = 0, N = Fields.size(); i < N; i++)
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FOS << "[" << i + 1 << "]: " << Fields[i] << "\n";
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FOS << "\n";
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for (unsigned i = 0, N = Paddings.size(); i < N; i++) {
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if (Paddings[i])
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FOS.PadToColumn(Paddings[i]);
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if (i < Fields.size())
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FOS << "[" << i + 1 << "]";
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else
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FOS << EndFields[i - Fields.size()];
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}
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FOS << "\n";
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for (const auto &[Index, IIVDEntry, Inst] : enumerate(IIVD, Source)) {
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FOS.PadToColumn(Paddings[0] + 1);
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FOS << IIVDEntry.NumMicroOpcodes;
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FOS.PadToColumn(Paddings[1] + 1);
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FOS << IIVDEntry.Latency;
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FOS.PadToColumn(Paddings[2]);
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if (IIVDEntry.RThroughput) {
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double RT = *IIVDEntry.RThroughput;
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FOS << format("%.2f", RT);
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} else {
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FOS << " -";
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}
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FOS.PadToColumn(Paddings[3] + 1);
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FOS << (IIVDEntry.mayLoad ? "*" : " ");
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FOS.PadToColumn(Paddings[4] + 1);
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FOS << (IIVDEntry.mayStore ? "*" : " ");
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FOS.PadToColumn(Paddings[5] + 1);
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FOS << (IIVDEntry.hasUnmodeledSideEffects ? "U" : " ");
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unsigned LastPaddingIdx = 5;
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if (PrintFullInfo) {
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
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FOS << IIVDEntry.Bypass;
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
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FOS << IIVDEntry.Resources;
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
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FOS << IIVDEntry.OpcodeName;
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}
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if (PrintBarriers) {
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
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FOS << (LoweredInsts[Index]->isALoadBarrier() ? "*" : " ");
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
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FOS << (LoweredInsts[Index]->isAStoreBarrier() ? "*" : " ");
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}
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if (PrintEncodings) {
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StringRef Encoding(CE.getEncoding(Index));
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unsigned EncodingSize = Encoding.size();
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
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FOS << EncodingSize;
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
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for (unsigned i = 0, e = Encoding.size(); i != e; ++i)
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FOS << format("%02x ", (uint8_t)Encoding[i]);
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}
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FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
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FOS << printInstructionString(Inst);
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if (PrintFullInfo) {
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FOS << "\t";
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getComment(FOS, Inst);
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}
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FOS << '\n';
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}
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OS << Buffer;
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}
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void InstructionInfoView::collectData(
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MutableArrayRef<InstructionInfoViewData> IIVD) const {
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const llvm::MCSubtargetInfo &STI = getSubTargetInfo();
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const MCSchedModel &SM = STI.getSchedModel();
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for (const auto I : zip(getSource(), IIVD)) {
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const MCInst &Inst = std::get<0>(I);
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InstructionInfoViewData &IIVDEntry = std::get<1>(I);
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const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
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// Obtain the scheduling class information from the instruction
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// and instruments.
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auto IVecIt = InstToInstruments.find(&Inst);
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unsigned SchedClassID =
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IVecIt == InstToInstruments.end()
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? MCDesc.getSchedClass()
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: IM.getSchedClassID(MCII, Inst, IVecIt->second);
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unsigned CPUID = SM.getProcessorID();
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// Try to solve variant scheduling classes.
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while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
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SchedClassID =
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STI.resolveVariantSchedClass(SchedClassID, &Inst, &MCII, CPUID);
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const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
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IIVDEntry.NumMicroOpcodes = SCDesc.NumMicroOps;
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IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
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// Add extra latency due to delays in the forwarding data paths.
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IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles(
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STI.getReadAdvanceEntries(SCDesc));
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IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc);
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IIVDEntry.mayLoad = MCDesc.mayLoad();
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IIVDEntry.mayStore = MCDesc.mayStore();
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IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
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if (PrintFullInfo) {
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// Get latency with bypass
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IIVDEntry.Bypass =
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IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc);
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IIVDEntry.OpcodeName = MCII.getName(Inst.getOpcode());
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raw_string_ostream TempStream(IIVDEntry.Resources);
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const MCWriteProcResEntry *Index = STI.getWriteProcResBegin(&SCDesc);
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const MCWriteProcResEntry *Last = STI.getWriteProcResEnd(&SCDesc);
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ListSeparator LS(",");
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for (; Index != Last; ++Index) {
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if (!Index->ReleaseAtCycle)
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continue;
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const MCProcResourceDesc *MCProc =
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SM.getProcResource(Index->ProcResourceIdx);
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if (Index->ReleaseAtCycle > 1) {
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// Output ReleaseAtCycle between [] if not 1 (default)
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// This is to be able to evaluate throughput.
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// See getReciprocalThroughput in MCSchedule.cpp
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if (Index->AcquireAtCycle > 0)
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TempStream << LS
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<< format("%s[%d,%d]", MCProc->Name,
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Index->AcquireAtCycle, Index->ReleaseAtCycle);
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else
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TempStream << LS
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<< format("%s[%d]", MCProc->Name, Index->ReleaseAtCycle);
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} else {
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TempStream << LS << MCProc->Name;
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}
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}
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}
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}
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}
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// Construct a JSON object from a single InstructionInfoViewData object.
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json::Object
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InstructionInfoView::toJSON(const InstructionInfoViewData &IIVD) const {
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json::Object JO({{"NumMicroOpcodes", IIVD.NumMicroOpcodes},
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{"Latency", IIVD.Latency},
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{"mayLoad", IIVD.mayLoad},
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{"mayStore", IIVD.mayStore},
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{"hasUnmodeledSideEffects", IIVD.hasUnmodeledSideEffects}});
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JO.try_emplace("RThroughput", IIVD.RThroughput.value_or(0.0));
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return JO;
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}
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json::Value InstructionInfoView::toJSON() const {
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ArrayRef<llvm::MCInst> Source = getSource();
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if (!Source.size())
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return json::Value(0);
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IIVDVec IIVD(Source.size());
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collectData(IIVD);
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json::Array InstInfo;
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for (const auto &I : enumerate(IIVD)) {
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const InstructionInfoViewData &IIVDEntry = I.value();
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json::Object JO = toJSON(IIVDEntry);
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JO.try_emplace("Instruction", (unsigned)I.index());
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InstInfo.push_back(std::move(JO));
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}
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return json::Object({{"InstructionList", json::Value(std::move(InstInfo))}});
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}
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} // namespace mca.
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} // namespace llvm
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