6dd14c881c
So that LoopStrengthReduce can work for MIPS. The code is copied from RISC-V. --------- Co-authored-by: qethu <190734095+qethu@users.noreply.github.com>
31 lines
1.4 KiB
C++
31 lines
1.4 KiB
C++
//===-- MipsTargetTransformInfo.cpp - Mips specific TTI ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetTransformInfo.h"
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using namespace llvm;
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bool MipsTTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
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EVT VT = TLI->getValueType(DL, DataType);
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return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
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VT);
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}
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bool MipsTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
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const TargetTransformInfo::LSRCost &C2) {
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// MIPS specific here are "instruction number 1st priority".
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// If we need to emit adds inside the loop to add up base registers, then
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// we need at least one extra temporary register.
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unsigned C1NumRegs = C1.NumRegs + (C1.NumBaseAdds != 0);
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unsigned C2NumRegs = C2.NumRegs + (C2.NumBaseAdds != 0);
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return std::tie(C1.Insns, C1NumRegs, C1.AddRecCost, C1.NumIVMuls,
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C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
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std::tie(C2.Insns, C2NumRegs, C2.AddRecCost, C2.NumIVMuls,
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C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
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}
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