0489447b07
The operand order of the assembly for dmr extract instructions has changed since they were added. The results now come before the uses.
263 lines
9.2 KiB
TableGen
263 lines
9.2 KiB
TableGen
//===-- PPCInstrFutureMMA.td - Future Instruction Set ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU for MMA.
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//
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//===----------------------------------------------------------------------===//
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class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<5> XAp;
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bits<5> XBp;
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bits<1> P;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-10} = 0;
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let Inst{11-14} = XAp{3-0};
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let Inst{15} = P;
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let Inst{16-19} = XBp{3-0};
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let Inst{20} = 0;
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let Inst{21-28} = xo;
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let Inst{29} = XAp{4};
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let Inst{30} = XBp{4};
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let Inst{31} = 0;
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}
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class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<5> XBp;
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bits<2> P;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-14} = 0;
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let Inst{15} = P{0};
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let Inst{16-19} = XBp{3-0};
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let Inst{20} = P{1};
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let Inst{21-29} = xo;
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let Inst{30} = XBp{4};
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let Inst{31} = 0;
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}
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class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I <opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<3> AT;
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bits<3> AB;
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let Pattern = pattern;
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let Inst{6-8} = AT{2-0};
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let Inst{9-10} = 0;
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let Inst{11-15} = o;
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let Inst{16-18} = AB{2-0};
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let Inst{19-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XX3Form_AT3_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<3> AT;
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bits<5> XAp;
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bits<6> XB;
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let Pattern = pattern;
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let Inst{6-8} = AT;
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let Inst{9-10} = 0;
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let Inst{11-14} = XAp{3-0};
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let Inst{15} = 0;
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let Inst{16-20} = XB{4-0};
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let Inst{21-28} = xo;
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let Inst{29} = XAp{4};
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let Inst{30} = XB{5};
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let Inst{31} = 0;
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}
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class MMIRR_XX3Form_X8YP4_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<3> AT;
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bits<6> XAp;
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bits<6> XB;
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bits<8> XMSK;
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bits<4> YMSK;
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bits<4> PMSK;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 3;
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let Inst{8-11} = 9;
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let Inst{12-15} = 0;
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let Inst{16-19} = PMSK;
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let Inst{20-27} = XMSK;
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let Inst{28-31} = YMSK;
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// The instruction.
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let Inst{38-40} = AT;
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let Inst{41-42} = 0;
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let Inst{43-46} = XAp{3-0};
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let Inst{47} = 0;
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let Inst{48-52} = XB{4-0};
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let Inst{53-60} = xo;
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let Inst{61} = XAp{4};
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let Inst{62} = XB{5};
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let Inst{63} = 0;
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}
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multiclass DMR_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
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string asmstr> {
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let Predicates = [MMA, IsISAFuture] in {
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def NAME :
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XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x01), (outs dmr:$AT), IOL,
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!strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
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RegConstraint<"@earlyclobber $AT">;
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def PP :
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XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
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!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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}
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multiclass DMR_UM_M448_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
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string asmstr> {
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defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def PM#NAME :
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MMIRR_XX3Form_X8YP4_XAp5B6<
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opcode, !or(xo, 0x01), (outs dmr:$AT),
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!con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
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!strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
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IIC_VecFP, []>,
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RegConstraint<"@earlyclobber $AT">;
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def PM#NAME#PP :
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MMIRR_XX3Form_X8YP4_XAp5B6<
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opcode, xo, (outs dmr:$AT),
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!con((ins dmr:$ATi),
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!con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
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!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
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IIC_VecFP, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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}
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let Predicates = [IsISAFuture] in {
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def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
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(ins wacc:$AT),
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"dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> {
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let P = 0;
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}
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def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
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(ins wacc_hi:$AT),
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"dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> {
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let P = 1;
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}
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def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
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(ins vsrprc:$XAp, vsrprc:$XBp),
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"dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
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let P = 0;
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}
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def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
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(ins vsrprc:$XAp, vsrprc:$XBp),
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"dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
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let P = 1;
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}
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def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
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(ins dmrrowp:$AT, u2imm:$P),
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"dmxxextfdmr256 $XBp, $AT, $P", []>;
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def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
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(ins vsrprc:$XBp, u2imm:$P),
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"dmxxinstfdmr256 $AT, $XBp, $P", []>;
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def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
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"dmmr $AT, $AB",
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[(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>;
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def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
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"dmxor $AT, $AB",
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[(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi, v1024i1:$AB))]>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
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"dmsetdmrz $AT", NoItinerary,
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[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
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}
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// MMA+ accumulating/non-accumulating instructions.
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// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
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defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4", "$AT, $XAp, $XB">;
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let Predicates = [MMA, IsISAFuture] in {
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def DMXVI8GERX4SPP :
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XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def PMDMXVI8GERX4SPP :
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MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT),
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(ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK,
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u4imm:$YMSK, u4imm:$PMSK),
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"pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
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IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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// MMA+ Intrinsics
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let Predicates = [MMA, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4 $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>;
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}
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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}
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