Brox Chen a61cc1b99a [AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918) ...

We only emits v_mov_b32/64_dpp. Don't combine t16 instructions with mov
dpp. Update the test inputs to be legal.

It is future work to emit v_mov_b16_dpp, and then update GCNDPPCombine
to combine it with the 16-bit instructions.

2025-03-31 10:18:25 -04:00

..

AArch64

[AArch64] Add bitcast + extend tests. NFC

2025-03-31 14:22:49 +01:00

AMDGPU

[AMDGPU][True16][CodeGen] Skip combineDpp with t16 instructions (#128918)

2025-03-31 10:18:25 -04:00

ARC

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ARM

[MC] Simplify MCBinaryExpr/MCUnaryExpr printing by reducing parentheses (#133674)

2025-03-30 22:03:14 -07:00

AVR

[AVR] Fix a bug in selection of ANY_EXTEND (#132398)

2025-03-26 15:15:40 +01:00

BPF

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CSKY

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DirectX

[DirectX] Remove intrinsic definitions with no use (#133459)

2025-03-29 00:45:11 -04:00

Generic

[YAML] fix output incorrect format for block scalar string (#132897)

2025-03-27 02:16:27 +08:00

Hexagon

[hexagon] Bump the default version to v68 (#132304)

2025-03-21 20:08:45 -05:00

Inputs

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Lanai

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LoongArch

[LoongArch] Custom lower vector trunc to vector shuffle (#130938)

2025-03-27 09:23:05 +08:00

M68k

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Mips

[MC] Don't print () around $ names

2025-03-30 16:38:16 -07:00

MIR

[YAML] fix output incorrect format for block scalar string (#132897)

2025-03-27 02:16:27 +08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Use fast-math flags when lowering sin, cos, frem (#133121)

2025-03-28 14:13:36 -07:00

PowerPC

[MC] Simplify MCBinaryExpr/MCUnaryExpr printing by reducing parentheses (#133674)

2025-03-30 22:03:14 -07:00

RISCV

[RISCV] Add combine for shadd family of instructions. (#130829)

2025-03-31 10:02:12 -04:00

SPARC

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SPIRV

[HLSL] Implement the smoothstep intrinsic (#132288)

2025-03-29 00:47:25 -04:00

SystemZ

[SystemZ] Add is(LoadFrom|StoreTo)StackSlotPostFE to SystemZBackend (#132928)

2025-03-25 15:03:54 +01:00

Thumb

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Thumb2

[MC] Simplify MCBinaryExpr/MCUnaryExpr printing by reducing parentheses (#133674)

2025-03-30 22:03:14 -07:00

VE

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WebAssembly

[WebAssembly] Lower wide SIMD i8 muls (#130785)

2025-03-21 06:57:57 +00:00

WinCFGuard

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WinEH

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X86

[X86] Add regression test for insert_subvector(x,extract_subvector(broadcast)) pattern identified in #133083

2025-03-31 15:01:31 +01:00

XCore

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Xtensa

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