Craig Topper 76f90a9d71 [SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift. ...

Otherwise we have garbage in the upper bits that can affect the
results of the UREM.

Fixes PR55296.

Differential Revision: https://reviews.llvm.org/D125076

2022-05-06 09:26:30 -07:00

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AArch64

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

AMDGPU

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

ARC

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ARM

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

AVR

[AVR] Always expand STDSPQRr & STDWSPQRr

2022-05-05 03:10:59 +00:00

BPF

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CSKY

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DirectX

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Generic

[NVPTX][tests] add "XFAIL: nvptx" for some tests

2022-04-26 17:26:56 +03:00

Hexagon

[NFC] Rename Instrinsic to Intrinsic

2022-04-25 18:13:23 +01:00

Inputs

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Lanai

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LoongArch

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M68k

[M68k] Regenerate cmp.ll tests

2022-04-21 16:54:00 +01:00

Mips

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

MIR

[X86] Check the address in machine verifier

2022-04-28 10:05:39 +08:00

MLRegalloc

[NVPTX][tests] Do not run the tests which are not supported by nvptx

2022-04-26 17:26:56 +03:00

MSP430

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NVPTX

[NVPTX] Prefix "$L__" for branch label names

2022-04-30 21:55:20 +02:00

PowerPC

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

RISCV

[RISCV] Add an extra vsetvli insertion test

2022-05-06 12:15:42 +01:00

SPARC

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SPIRV

[SPIRV] Add SPIR-V specific intrinsics, two passes and tests

2022-05-06 03:02:00 +03:00

SystemZ

[SelectionDAG] Constant fold (sext_inreg undef, VT) to 0 instead of undef.

2022-05-05 09:45:35 -07:00

Thumb

[ARM] Only update the successor edges for immediate predecessors of PrologueMBB

2022-05-03 12:36:35 +01:00

Thumb2

[DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask'))

2022-05-06 10:50:31 +01:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntRes_FunnelShift.

2022-05-06 09:26:30 -07:00

XCore

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