7d52565321
Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188179
41 lines
1.7 KiB
LLVM
41 lines
1.7 KiB
LLVM
; This provides optimized implementations of vstore2/3/4/8/16 for 32-bit int/uint
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; The address spaces get mapped to data types in target-specific usages
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define void @__clc_vstore2_i32__addr1(<2 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
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%1 = bitcast i32 addrspace(1)* %addr to <2 x i32> addrspace(1)*
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store <2 x i32> %vec, <2 x i32> addrspace(1)* %1, align 4, !tbaa !3
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ret void
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}
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define void @__clc_vstore3_i32__addr1(<3 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
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%1 = bitcast i32 addrspace(1)* %addr to <3 x i32> addrspace(1)*
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store <3 x i32> %vec, <3 x i32> addrspace(1)* %1, align 4, !tbaa !3
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ret void
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}
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define void @__clc_vstore4_i32__addr1(<4 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
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%1 = bitcast i32 addrspace(1)* %addr to <4 x i32> addrspace(1)*
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store <4 x i32> %vec, <4 x i32> addrspace(1)* %1, align 4, !tbaa !3
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ret void
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}
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define void @__clc_vstore8_i32__addr1(<8 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
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%1 = bitcast i32 addrspace(1)* %addr to <8 x i32> addrspace(1)*
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store <8 x i32> %vec, <8 x i32> addrspace(1)* %1, align 4, !tbaa !3
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ret void
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}
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define void @__clc_vstore16_i32__addr1(<16 x i32> %vec, i32 addrspace(1)* nocapture %addr) nounwind alwaysinline {
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%1 = bitcast i32 addrspace(1)* %addr to <16 x i32> addrspace(1)*
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store <16 x i32> %vec, <16 x i32> addrspace(1)* %1, align 4, !tbaa !3
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ret void
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}
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!1 = metadata !{metadata !"char", metadata !5}
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!2 = metadata !{metadata !"short", metadata !5}
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!3 = metadata !{metadata !"int", metadata !5}
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!4 = metadata !{metadata !"long", metadata !5}
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!5 = metadata !{metadata !"omnipotent char", metadata !6}
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!6 = metadata !{metadata !"Simple C/C++ TBAA"}
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