b410d24a19
Thispatch implements the R_RISCV_ADD32 and R_RISCV_SUB32 relocations for RISC-V. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D146554
24 lines
528 B
ArmAsm
24 lines
528 B
ArmAsm
// RUN: %clang %cflags -o %t %s
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// RUN: llvm-bolt -o %t.bolt %t
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// RUN: llvm-readelf -x .data %t.bolt | FileCheck %s
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.text
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.option norvc
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.globl _start
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.p2align 1
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_start:
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// Force BOLT into relocation mode
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.reloc 0, R_RISCV_NONE
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// BOLT removes this nop so the label difference is initially 8 but should be
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// 4 after BOLT processes it.
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nop
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beq x0, x0, _test_end
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_test_end:
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ret
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.size _start, .-_start
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.data
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// CHECK: Hex dump of section '.data':
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// CHECK: 0x{{.*}} 04000000
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.word _test_end - _start
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