eae26b6640
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as an integer so we may as well use the prefered form from creation. NOTE: All test changes are mechanical with nothing else expected beyond a change of index type from i32 to i64. Differential Revision: https://reviews.llvm.org/D140983
341 lines
9.9 KiB
C
341 lines
9.9 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
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// RUN: -disable-O0-optnone \
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// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sve.h>
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// AND
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// CHECK-LABEL: @and_bool(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[AND]]
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//
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svbool_t and_bool(svbool_t a, svbool_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_i8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[AND]]
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//
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svint8_t and_i8(svint8_t a, svint8_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_i16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[AND]]
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//
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svint16_t and_i16(svint16_t a, svint16_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_i32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[AND]]
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//
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svint32_t and_i32(svint32_t a, svint32_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_i64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[AND]]
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//
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svint64_t and_i64(svint64_t a, svint64_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[AND]]
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//
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svuint8_t and_u8(svuint8_t a, svuint8_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[AND]]
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//
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svuint16_t and_u16(svuint16_t a, svuint16_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[AND]]
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//
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svuint32_t and_u32(svuint32_t a, svuint32_t b) {
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return a & b;
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}
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// CHECK-LABEL: @and_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[AND:%.*]] = and <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[AND]]
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//
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svuint64_t and_u64(svuint64_t a, svuint64_t b) {
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return a & b;
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}
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// OR
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// CHECK-LABEL: @or_bool(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[OR]]
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//
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svbool_t or_bool(svbool_t a, svbool_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_i8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[OR]]
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//
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svint8_t or_i8(svint8_t a, svint8_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_i16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[OR]]
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//
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svint16_t or_i16(svint16_t a, svint16_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_i32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[OR]]
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//
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svint32_t or_i32(svint32_t a, svint32_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_i64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[OR]]
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//
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svint64_t or_i64(svint64_t a, svint64_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[OR]]
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//
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svuint8_t or_u8(svuint8_t a, svuint8_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[OR]]
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//
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svuint16_t or_u16(svuint16_t a, svuint16_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[OR]]
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//
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svuint32_t or_u32(svuint32_t a, svuint32_t b) {
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return a | b;
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}
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// CHECK-LABEL: @or_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OR:%.*]] = or <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[OR]]
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//
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svuint64_t or_u64(svuint64_t a, svuint64_t b) {
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return a | b;
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}
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// XOR
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// CHECK-LABEL: @xor_bool(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[XOR]]
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//
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svbool_t xor_bool(svbool_t a, svbool_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_i8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[XOR]]
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//
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svint8_t xor_i8(svint8_t a, svint8_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_i16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[XOR]]
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//
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svint16_t xor_i16(svint16_t a, svint16_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_i32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[XOR]]
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//
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svint32_t xor_i32(svint32_t a, svint32_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_i64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[XOR]]
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//
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svint64_t xor_i64(svint64_t a, svint64_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[XOR]]
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//
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svuint8_t xor_u8(svuint8_t a, svuint8_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[XOR]]
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//
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svuint16_t xor_u16(svuint16_t a, svuint16_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[XOR]]
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//
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svuint32_t xor_u32(svuint32_t a, svuint32_t b) {
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return a ^ b;
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}
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// CHECK-LABEL: @xor_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[XOR:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[XOR]]
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//
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svuint64_t xor_u64(svuint64_t a, svuint64_t b) {
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return a ^ b;
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}
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// NEG
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// CHECK-LABEL: @neg_bool(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i64 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[NEG]]
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//
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svbool_t neg_bool(svbool_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
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//
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svint8_t neg_i8(svint8_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
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//
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svint16_t neg_i16(svint16_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
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//
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svint32_t neg_i32(svint32_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_i64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
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//
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svint64_t neg_i64(svint64_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
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//
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svuint8_t neg_u8(svuint8_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
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//
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svuint16_t neg_u16(svuint16_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
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//
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svuint32_t neg_u32(svuint32_t a) {
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return ~a;
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}
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// CHECK-LABEL: @neg_u64(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
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//
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svuint64_t neg_u64(svuint64_t a) {
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return ~a;
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}
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