03ef89f8d9
This patch contains several related changes: 1. We move to using TARGET_BUILTIN for the 128-bit system register builtins to give better error messages when d128 has not been enabled, or has been enabled in a per-function manner. 2. We now validate the inputs to the 128-bit system register builtins, like we validate the other system register builtins. 3. We update the list of named PSTATE accessors for MSR (immediate), and now correctly enforce the expected ranges of the immediates. There is a long comment about how we chose to do this to comply with the ACLE when most of the PSTATE accessors for MSR (immediate) have aliased system registers for MRS/MSR which expect different values. In short, the MSR (immediate) names are prioritised, rather than falling-back to the register form when the value is out of range. Differential Revision: https://reviews.llvm.org/D140222
33 lines
1.0 KiB
C
33 lines
1.0 KiB
C
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +v8a -fsyntax-only -verify -emit-llvm -o - %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +d128 -fsyntax-only -verify=d128 -emit-llvm -o - %s
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// REQUIRES: aarch64-registered-target
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// Test that functions with the correct target attributes can use the correct
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// system-register intriniscs.
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// All the calls below are valid if you have -target-feature +d128
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// d128-no-diagnostics
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#include <arm_acle.h>
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void anytarget(void) {
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unsigned x = __arm_rsr("1:2:3:4:5");
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__arm_wsr("1:2:3:4:5", x);
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unsigned long y = __arm_rsr64("1:2:3:4:5");
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__arm_wsr64("1:2:3:4:5", y);
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void *p = __arm_rsrp("1:2:3:4:5");
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__arm_wsrp("1:2:3:4:5", p);
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}
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__attribute__((target("d128")))
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void d128target(void) {
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__uint128_t x = __arm_rsr128("1:2:3:4:5");
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__arm_wsr128("1:2:3:4:5", x);
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}
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void notd128target(void) {
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__uint128_t x = __arm_rsr128("1:2:3:4:5"); // expected-error {{needs target feature d128}}
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__arm_wsr128("1:2:3:4:5", x); // expected-error {{needs target feature d128}}
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}
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