b879f99f0e
Similar to D131064, this alters most of the intrinsics in arm_neon.h to be target based, not preprocessor based. The intrinsics that are changed are the ones with obvious target features (fp16, fp16fml, cryptos, i8mm and bf16). The ones that are not yet altered are the ones without target features like rdma (8.1) and complex (8.3). Those will be switched in a followup patch that allows targeting architecture versions. The existing ArchGuard in arm_neon.td is split into ArchGuard that still adds ifdef defines (for example for intrinsics that require __aarch64__), and TargetGuards for intrinsics dependant on target features. From there the TargetGuards are used in two ways: - For intrinsics emitted as functions, __attribute__((target(TargetGuard))) is added to the definition of the function. Along with the existing always_inline intrinsic, this will give a compile time error if the function is used in a context where the target feature is not available. - For intrinsics emitted as macros, the __builtins are emitted into arm_neon.inc using TARGET_BUILTIN as opposed to BUILTIN, which includes the target feature and gives an error if the builtin is found in a function without the required features, similar to arm_sve.h. The second method requires that the intrinsics be separable from the existing _v intrinsics used in other types. For example __builtin_neon_splat_lane_bf16 is used as opposed to __builtin_neon_splat_lane_v. There are some adjustments to the CGBuiltin to account for intrinsics that can be treated similarly, except for their target features. Differential Revision: https://reviews.llvm.org/D132034
99 lines
4.2 KiB
C
99 lines
4.2 KiB
C
// RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \
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// RUN: -target-feature +sha2 -target-feature +aes \
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// RUN: -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -target-feature +sha2 -target-feature +aes \
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// RUN: -emit-llvm -O1 -o - %s | FileCheck %s
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// RUN: not %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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// RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) {
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// CHECK-LABEL: @test_vaeseq_u8
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// CHECK-NO-CRYPTO: error: always_inline function 'vaeseq_u8' requires target feature 'aes'
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return vaeseq_u8(data, key);
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// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aese(<16 x i8> %data, <16 x i8> %key)
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}
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uint8x16_t test_vaesdq_u8(uint8x16_t data, uint8x16_t key) {
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// CHECK-LABEL: @test_vaesdq_u8
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return vaesdq_u8(data, key);
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// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesd(<16 x i8> %data, <16 x i8> %key)
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}
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uint8x16_t test_vaesmcq_u8(uint8x16_t data) {
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// CHECK-LABEL: @test_vaesmcq_u8
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return vaesmcq_u8(data);
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// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesmc(<16 x i8> %data)
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}
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uint8x16_t test_vaesimcq_u8(uint8x16_t data) {
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// CHECK-LABEL: @test_vaesimcq_u8
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return vaesimcq_u8(data);
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// CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesimc(<16 x i8> %data)
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}
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uint32_t test_vsha1h_u32(uint32_t hash_e) {
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// CHECK-LABEL: @test_vsha1h_u32
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return vsha1h_u32(hash_e);
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// CHECK: call i32 @llvm.{{arm.neon|aarch64.crypto}}.sha1h(i32 %hash_e)
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}
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uint32x4_t test_vsha1su1q_u32(uint32x4_t w0_3, uint32x4_t w12_15) {
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// CHECK-LABEL: @test_vsha1su1q_u32
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return vsha1su1q_u32(w0_3, w12_15);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su1(<4 x i32> %w0_3, <4 x i32> %w12_15)
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}
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uint32x4_t test_vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7) {
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// CHECK-LABEL: @test_vsha256su0q_u32
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return vsha256su0q_u32(w0_3, w4_7);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
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}
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uint32x4_t test_vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK-LABEL: @test_vsha1cq_u32
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return vsha1cq_u32(hash_abcd, hash_e, wk);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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}
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uint32x4_t test_vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK-LABEL: @test_vsha1pq_u32
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return vsha1pq_u32(hash_abcd, hash_e, wk);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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}
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uint32x4_t test_vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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// CHECK-LABEL: @test_vsha1mq_u32
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return vsha1mq_u32(hash_abcd, hash_e, wk);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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}
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uint32x4_t test_vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) {
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// CHECK-LABEL: @test_vsha1su0q_u32
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return vsha1su0q_u32(w0_3, w4_7, w8_11);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
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}
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uint32x4_t test_vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) {
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// CHECK-LABEL: @test_vsha256hq_u32
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return vsha256hq_u32(hash_abcd, hash_efgh, wk);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
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}
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uint32x4_t test_vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) {
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// CHECK-LABEL: @test_vsha256h2q_u32
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return vsha256h2q_u32(hash_efgh, hash_abcd, wk);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
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}
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uint32x4_t test_vsha256su1q_u32(uint32x4_t w0_3, uint32x4_t w8_11, uint32x4_t w12_15) {
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// CHECK-LABEL: @test_vsha256su1q_u32
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return vsha256su1q_u32(w0_3, w8_11, w12_15);
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// CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
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}
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