92bbf615f5
This patch removes the omp.target module attribute, since the information it held on the target CPU and features is available through the fir.target_cpu and fir.target_features module attributes. Target outlining during the MLIR to LLVM IR translation stage is updated, so that these attributes, at that point available as llvm.func attributes, are passed along to the newly created function.
20 lines
1.2 KiB
Fortran
20 lines
1.2 KiB
Fortran
!REQUIRES: amdgpu-registered-target, nvptx-registered-target
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!RUN: %flang_fc1 -emit-hlfir -triple amdgcn-amd-amdhsa -target-cpu gfx908 -fopenmp -fopenmp-is-target-device %s -o - | FileCheck --check-prefix=AMDGCN %s
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!RUN: %flang_fc1 -emit-hlfir -triple nvptx64-nvidia-cuda -target-cpu sm_80 -fopenmp -fopenmp-is-target-device %s -o - | FileCheck --check-prefix=NVPTX %s
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!===============================================================================
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! Target_Enter Simple
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!===============================================================================
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!AMDGCN: module attributes {
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!AMDGCN-SAME: fir.target_cpu = "gfx908"
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!AMDGCN-SAME: fir.target_features = #llvm.target_features<["+16-bit-insts", "+ci-insts",
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!AMDGCN-SAME: "+dl-insts", "+dot1-insts", "+dot10-insts", "+dot2-insts", "+dot3-insts",
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!AMDGCN-SAME: "+dot4-insts", "+dot5-insts", "+dot6-insts", "+dot7-insts", "+dpp",
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!AMDGCN-SAME: "+gfx8-insts", "+gfx9-insts", "+gws", "+image-insts", "+mai-insts",
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!AMDGCN-SAME: "+s-memrealtime", "+s-memtime-inst", "+wavefrontsize64"]>
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!NVPTX: module attributes {
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!NVPTX-SAME: fir.target_cpu = "sm_80"
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!NVPTX-SAME: fir.target_features = #llvm.target_features<["+ptx61", "+sm_80"]>
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