4888218d03
In some cases, the machine outliner needs to preserve LR across an outlined call by pushing it onto the stack. Previously, this also generated unwind table instructions, which is incorrect because EHABI unwind tables cannot represent different stack frames a different points in the function, so the extra unwind info applied to the entire function. The outliner code already avoided generating CFI instructions, but EHABI unwind data is generated later from the actual instructions, so we need to avoid using the FrameSetup and FrameDestroy flags to prevent unwind data being generated.
121 lines
4.3 KiB
C++
121 lines
4.3 KiB
C++
//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#include "ARMSubtarget.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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#include <optional>
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namespace llvm {
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class ARMBaseTargetMachine : public LLVMTargetMachine {
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public:
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enum ARMABI {
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ARM_ABI_UNKNOWN,
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ARM_ABI_APCS,
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ARM_ABI_AAPCS, // ARM EABI
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ARM_ABI_AAPCS16
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} TargetABI;
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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bool isLittle;
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mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
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public:
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ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool isLittle);
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~ARMBaseTargetMachine() override;
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const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
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// DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
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// subtargets are per-function entities based on the target-specific
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// attributes of each function.
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const ARMSubtarget *getSubtargetImpl() const = delete;
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bool isLittleEndian() const { return isLittle; }
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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bool isTargetHardFloat() const {
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return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
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TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
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TargetTriple.getEnvironment() == Triple::EABIHF ||
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(TargetTriple.isOSBinFormatMachO() &&
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TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
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TargetTriple.isOSWindows() ||
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TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
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}
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bool targetSchedulesPostRAScheduling() const override { return true; };
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
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yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const override;
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bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const override;
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};
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/// ARM/Thumb little endian target machine.
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///
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class ARMLETargetMachine : public ARMBaseTargetMachine {
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public:
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ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool JIT);
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};
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/// ARM/Thumb big endian target machine.
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///
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class ARMBETargetMachine : public ARMBaseTargetMachine {
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public:
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ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool JIT);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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