bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
246 lines
8.8 KiB
C++
246 lines
8.8 KiB
C++
//===- LanaiDisassembler.cpp - Disassembler for Lanai -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Lanai Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiDisassembler.h"
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#include "LanaiAluCode.h"
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#include "LanaiCondCode.h"
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#include "LanaiInstrInfo.h"
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#include "TargetInfo/LanaiTargetInfo.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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static MCDisassembler *createLanaiDisassembler(const Target & /*T*/,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new LanaiDisassembler(STI, Ctx);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiDisassembler() {
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// Register the disassembler
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TargetRegistry::RegisterMCDisassembler(getTheLanaiTarget(),
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createLanaiDisassembler);
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}
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LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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// Forward declare because the autogenerated code will reference this.
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// Definition is further down.
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder);
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#include "LanaiGenDisassemblerTables.inc"
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static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t &Size,
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uint32_t &Insn) {
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// We want to read exactly 4 bytes of data.
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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// Encoded as big-endian 32-bit word in the stream.
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Insn =
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(Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
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return MCDisassembler::Success;
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}
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static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) {
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unsigned AluOp = LPAC::ADD;
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// Fix up for pre and post operations.
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int PqShift = -1;
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if (isRMOpcode(Instr.getOpcode()))
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PqShift = 16;
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else if (isSPLSOpcode(Instr.getOpcode()))
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PqShift = 10;
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else if (isRRMOpcode(Instr.getOpcode())) {
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PqShift = 16;
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// Determine RRM ALU op.
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AluOp = (Insn >> 8) & 0x7;
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if (AluOp == 7)
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// Handle JJJJJ
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// 0b10000 or 0b11000
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AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1);
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}
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if (PqShift != -1) {
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unsigned PQ = (Insn >> PqShift) & 0x3;
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switch (PQ) {
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case 0x0:
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if (Instr.getOperand(2).isReg()) {
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Instr.getOperand(2).setReg(Lanai::R0);
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}
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if (Instr.getOperand(2).isImm())
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Instr.getOperand(2).setImm(0);
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break;
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case 0x1:
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AluOp = LPAC::makePostOp(AluOp);
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break;
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case 0x2:
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break;
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case 0x3:
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AluOp = LPAC::makePreOp(AluOp);
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break;
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}
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Instr.addOperand(MCOperand::createImm(AluOp));
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}
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}
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DecodeStatus
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LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream & /*CStream*/) const {
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uint32_t Insn;
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DecodeStatus Result = readInstruction32(Bytes, Size, Insn);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Call auto-generated decoder function
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Result =
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decodeInstruction(DecoderTableLanai32, Instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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PostOperandDecodeAdjust(Instr, Insn);
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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static const unsigned GPRDecoderTable[] = {
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Lanai::R0, Lanai::R1, Lanai::PC, Lanai::R3, Lanai::SP, Lanai::FP,
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Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
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Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
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Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
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Lanai::R30, Lanai::R31};
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DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t /*Address*/,
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const MCDisassembler * /*Decoder*/) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = GPRDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// RI memory values encoded using 23 bits:
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// 5 bit register, 16 bit constant
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unsigned Register = (Insn >> 18) & 0x1f;
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Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
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unsigned Offset = (Insn & 0xffff);
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Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// RR memory values encoded using 20 bits:
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// 5 bit register, 5 bit register, 2 bit PQ, 3 bit ALU operator, 5 bit JJJJJ
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unsigned Register = (Insn >> 15) & 0x1f;
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Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
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Register = (Insn >> 10) & 0x1f;
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Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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// RI memory values encoded using 17 bits:
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// 5 bit register, 10 bit constant
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unsigned Register = (Insn >> 12) & 0x1f;
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Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
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unsigned Offset = (Insn & 0x3ff);
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Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
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return MCDisassembler::Success;
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool IsBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const MCDisassembler *Decoder) {
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return Decoder->tryAddingSymbolicOperand(MI, Value, Address, IsBranch, Offset,
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Width, /*InstSize=*/0);
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}
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static DecodeStatus decodeBranch(MCInst &MI, unsigned Insn, uint64_t Address,
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const MCDisassembler *Decoder) {
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if (!tryAddingSymbolicOperand(Insn + Address, false, Address, 2, 23, MI,
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Decoder))
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MI.addOperand(MCOperand::createImm(Insn));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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unsigned Offset = (Insn & 0xffff);
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Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodePredicateOperand(MCInst &Inst, unsigned Val,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (Val >= LPCC::UNKNOWN)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Val));
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return MCDisassembler::Success;
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}
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