2cf420d5b8
According to the description of the psABI v2.20: https://github.com/loongson/la-abi-specs/releases/tag/v2.20, adjustments are made to the function call instructions under the medium code model. At the same time, AsmParser has already supported parsing the call36 and tail36 macro instructions.
358 lines
13 KiB
C++
358 lines
13 KiB
C++
//=- LoongArchMCCodeEmitter.cpp - Convert LoongArch code to machine code --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LoongArchMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchFixupKinds.h"
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#include "MCTargetDesc/LoongArchBaseInfo.h"
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#include "MCTargetDesc/LoongArchMCExpr.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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namespace {
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class LoongArchMCCodeEmitter : public MCCodeEmitter {
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LoongArchMCCodeEmitter(const LoongArchMCCodeEmitter &) = delete;
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void operator=(const LoongArchMCCodeEmitter &) = delete;
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MCContext &Ctx;
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MCInstrInfo const &MCII;
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public:
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LoongArchMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
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: Ctx(ctx), MCII(MCII) {}
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~LoongArchMCCodeEmitter() override {}
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void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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template <unsigned Opc>
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void expandToVectorLDI(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// TableGen'erated function for getting the binary encoding for an
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/// instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of operand. If the machine operand requires
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/// relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of an immediate operand specified by OpNo.
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/// The value returned is the value of the immediate minus 1.
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/// Note that this function is dedicated to specific immediate types,
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/// e.g. uimm2_plus1.
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unsigned getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of an immediate operand specified by OpNo.
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/// The value returned is the value of the immediate shifted right
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// arithmetically by N.
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/// Note that this function is dedicated to specific immediate types,
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/// e.g. simm14_lsl2, simm16_lsl2, simm21_lsl2 and simm26_lsl2.
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template <unsigned N>
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unsigned getImmOpValueAsr(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm()) {
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unsigned Res = MI.getOperand(OpNo).getImm();
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assert((Res & ((1U << N) - 1U)) == 0 && "lowest N bits are non-zero");
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return Res >> N;
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}
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return getExprOpValue(MI, MO, Fixups, STI);
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}
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unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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};
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} // end namespace
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unsigned
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LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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// MO must be an Expr.
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assert(MO.isExpr());
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return getExprOpValue(MI, MO, Fixups, STI);
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}
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unsigned
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LoongArchMCCodeEmitter::getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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return MI.getOperand(OpNo).getImm() - 1;
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}
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unsigned
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LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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assert(MO.isExpr() && "getExprOpValue expects only expressions");
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bool RelaxCandidate = false;
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bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
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if (Kind == MCExpr::Target) {
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const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
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RelaxCandidate = LAExpr->getRelaxHint();
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switch (LAExpr->getKind()) {
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case LoongArchMCExpr::VK_LoongArch_None:
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case LoongArchMCExpr::VK_LoongArch_Invalid:
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llvm_unreachable("Unhandled fixup kind!");
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case LoongArchMCExpr::VK_LoongArch_B16:
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FixupKind = LoongArch::fixup_loongarch_b16;
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break;
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case LoongArchMCExpr::VK_LoongArch_B21:
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FixupKind = LoongArch::fixup_loongarch_b21;
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break;
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case LoongArchMCExpr::VK_LoongArch_B26:
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case LoongArchMCExpr::VK_LoongArch_CALL:
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case LoongArchMCExpr::VK_LoongArch_CALL_PLT:
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FixupKind = LoongArch::fixup_loongarch_b26;
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break;
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case LoongArchMCExpr::VK_LoongArch_ABS_HI20:
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FixupKind = LoongArch::fixup_loongarch_abs_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_ABS_LO12:
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FixupKind = LoongArch::fixup_loongarch_abs_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_ABS64_LO20:
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FixupKind = LoongArch::fixup_loongarch_abs64_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_ABS64_HI12:
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FixupKind = LoongArch::fixup_loongarch_abs64_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_PCALA_HI20:
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FixupKind = LoongArch::fixup_loongarch_pcala_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_PCALA_LO12:
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FixupKind = LoongArch::fixup_loongarch_pcala_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_PCALA64_LO20:
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FixupKind = LoongArch::fixup_loongarch_pcala64_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_PCALA64_HI12:
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FixupKind = LoongArch::fixup_loongarch_pcala64_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT_PC_HI20:
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FixupKind = LoongArch::fixup_loongarch_got_pc_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12:
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FixupKind = LoongArch::fixup_loongarch_got_pc_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT64_PC_LO20:
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FixupKind = LoongArch::fixup_loongarch_got64_pc_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT64_PC_HI12:
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FixupKind = LoongArch::fixup_loongarch_got64_pc_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT_HI20:
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FixupKind = LoongArch::fixup_loongarch_got_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT_LO12:
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FixupKind = LoongArch::fixup_loongarch_got_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT64_LO20:
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FixupKind = LoongArch::fixup_loongarch_got64_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_GOT64_HI12:
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FixupKind = LoongArch::fixup_loongarch_got64_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_le_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12:
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FixupKind = LoongArch::fixup_loongarch_tls_le_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LE64_LO20:
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FixupKind = LoongArch::fixup_loongarch_tls_le64_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LE64_HI12:
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FixupKind = LoongArch::fixup_loongarch_tls_le64_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_LO12:
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FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_LO20:
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FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_HI12:
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FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_ie_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE_LO12:
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FixupKind = LoongArch::fixup_loongarch_tls_ie_lo12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE64_LO20:
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FixupKind = LoongArch::fixup_loongarch_tls_ie64_lo20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_IE64_HI12:
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FixupKind = LoongArch::fixup_loongarch_tls_ie64_hi12;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LD_PC_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_ld_pc_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_LD_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_ld_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_GD_PC_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_gd_pc_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_TLS_GD_HI20:
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FixupKind = LoongArch::fixup_loongarch_tls_gd_hi20;
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break;
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case LoongArchMCExpr::VK_LoongArch_CALL36:
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FixupKind = LoongArch::fixup_loongarch_call36;
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break;
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}
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} else if (Kind == MCExpr::SymbolRef &&
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cast<MCSymbolRefExpr>(Expr)->getKind() ==
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MCSymbolRefExpr::VK_None) {
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switch (MI.getOpcode()) {
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default:
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break;
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case LoongArch::BEQ:
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case LoongArch::BNE:
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case LoongArch::BLT:
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case LoongArch::BGE:
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case LoongArch::BLTU:
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case LoongArch::BGEU:
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FixupKind = LoongArch::fixup_loongarch_b16;
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break;
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case LoongArch::BEQZ:
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case LoongArch::BNEZ:
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case LoongArch::BCEQZ:
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case LoongArch::BCNEZ:
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FixupKind = LoongArch::fixup_loongarch_b21;
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break;
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case LoongArch::B:
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case LoongArch::BL:
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FixupKind = LoongArch::fixup_loongarch_b26;
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break;
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}
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}
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assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
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"Unhandled expression!");
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Fixups.push_back(
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MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
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// Emit an R_LARCH_RELAX if linker relaxation is enabled and LAExpr has relax
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// hint.
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if (EnableRelax && RelaxCandidate) {
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const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
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Fixups.push_back(MCFixup::create(
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0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
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}
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return 0;
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}
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template <unsigned Opc>
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void LoongArchMCCodeEmitter::expandToVectorLDI(
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const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
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int64_t Imm = MI.getOperand(1).getImm() & 0x3FF;
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switch (MI.getOpcode()) {
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case LoongArch::PseudoVREPLI_B:
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case LoongArch::PseudoXVREPLI_B:
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break;
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case LoongArch::PseudoVREPLI_H:
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case LoongArch::PseudoXVREPLI_H:
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Imm |= 0x400;
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break;
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case LoongArch::PseudoVREPLI_W:
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case LoongArch::PseudoXVREPLI_W:
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Imm |= 0x800;
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break;
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case LoongArch::PseudoVREPLI_D:
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case LoongArch::PseudoXVREPLI_D:
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Imm |= 0xC00;
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break;
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}
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MCInst TmpInst = MCInstBuilder(Opc).addOperand(MI.getOperand(0)).addImm(Imm);
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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}
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void LoongArchMCCodeEmitter::encodeInstruction(
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const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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// Get byte count of instruction.
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unsigned Size = Desc.getSize();
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switch (MI.getOpcode()) {
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default:
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break;
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case LoongArch::PseudoVREPLI_B:
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case LoongArch::PseudoVREPLI_H:
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case LoongArch::PseudoVREPLI_W:
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case LoongArch::PseudoVREPLI_D:
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return expandToVectorLDI<LoongArch::VLDI>(MI, CB, Fixups, STI);
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case LoongArch::PseudoXVREPLI_B:
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case LoongArch::PseudoXVREPLI_H:
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case LoongArch::PseudoXVREPLI_W:
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case LoongArch::PseudoXVREPLI_D:
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return expandToVectorLDI<LoongArch::XVLDI>(MI, CB, Fixups, STI);
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}
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switch (Size) {
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default:
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llvm_unreachable("Unhandled encodeInstruction length!");
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case 4: {
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uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write(CB, Bits, llvm::endianness::little);
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break;
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}
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}
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}
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MCCodeEmitter *llvm::createLoongArchMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new LoongArchMCCodeEmitter(Ctx, MCII);
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}
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#include "LoongArchGenMCCodeEmitter.inc"
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