601e102bdb
This is part of #70452 that changes the type used for the external interface of MMO to LocationSize as opposed to uint64_t. This means the constructors take LocationSize, and convert ~UINT64_C(0) to LocationSize::beforeOrAfter(). The getSize methods return a LocationSize. This allows us to be more precise with unknown sizes, not accidentally treating them as unsigned values, and in the future should allow us to add proper scalable vector support but none of that is included in this patch. It should mostly be an NFC. Global ISel is still expected to use the underlying LLT as it needs, and are not expected to see unknown sizes for generic operations. Most of the changes are hopefully fairly mechanical, adding a lot of getValue() calls and protecting them with hasValue() where needed.
936 lines
34 KiB
C++
936 lines
34 KiB
C++
//===- MipsInstructionSelector.cpp ------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// Mips.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterBankInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/IR/IntrinsicsMips.h"
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#define DEBUG_TYPE "mips-isel"
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using namespace llvm;
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class MipsInstructionSelector : public InstructionSelector {
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public:
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MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
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const MipsRegisterBankInfo &RBI);
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bool select(MachineInstr &I) override;
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static const char *getName() { return DEBUG_TYPE; }
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private:
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool isRegInGprb(Register Reg, MachineRegisterInfo &MRI) const;
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bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
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bool materialize32BitImm(Register DestReg, APInt Imm,
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MachineIRBuilder &B) const;
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bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
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const TargetRegisterClass *
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getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
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unsigned selectLoadStoreOpCode(MachineInstr &I,
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MachineRegisterInfo &MRI) const;
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bool buildUnalignedStore(MachineInstr &I, unsigned Opc,
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MachineOperand &BaseAddr, unsigned Offset,
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MachineMemOperand *MMO) const;
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bool buildUnalignedLoad(MachineInstr &I, unsigned Opc, Register Dest,
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MachineOperand &BaseAddr, unsigned Offset,
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Register TiedDest, MachineMemOperand *MMO) const;
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const MipsTargetMachine &TM;
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const MipsSubtarget &STI;
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const MipsInstrInfo &TII;
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const MipsRegisterInfo &TRI;
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const MipsRegisterBankInfo &RBI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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MipsInstructionSelector::MipsInstructionSelector(
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const MipsTargetMachine &TM, const MipsSubtarget &STI,
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const MipsRegisterBankInfo &RBI)
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: TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
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RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "MipsGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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bool MipsInstructionSelector::isRegInGprb(Register Reg,
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MachineRegisterInfo &MRI) const {
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return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
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}
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bool MipsInstructionSelector::isRegInFprb(Register Reg,
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MachineRegisterInfo &MRI) const {
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return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
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}
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bool MipsInstructionSelector::selectCopy(MachineInstr &I,
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MachineRegisterInfo &MRI) const {
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Register DstReg = I.getOperand(0).getReg();
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if (DstReg.isPhysical())
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return true;
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const TargetRegisterClass *RC = getRegClassForTypeOnBank(DstReg, MRI);
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if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
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<< " operand\n");
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return false;
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}
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return true;
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}
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const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank(
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Register Reg, MachineRegisterInfo &MRI) const {
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const LLT Ty = MRI.getType(Reg);
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const unsigned TySize = Ty.getSizeInBits();
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if (isRegInGprb(Reg, MRI)) {
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assert((Ty.isScalar() || Ty.isPointer()) && TySize == 32 &&
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"Register class not available for LLT, register bank combination");
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return &Mips::GPR32RegClass;
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}
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if (isRegInFprb(Reg, MRI)) {
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if (Ty.isScalar()) {
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assert((TySize == 32 || TySize == 64) &&
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"Register class not available for LLT, register bank combination");
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if (TySize == 32)
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return &Mips::FGR32RegClass;
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return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
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}
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}
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llvm_unreachable("Unsupported register bank.");
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}
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bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
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MachineIRBuilder &B) const {
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assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
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// Ori zero extends immediate. Used for values with zeros in high 16 bits.
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if (Imm.getHiBits(16).isZero()) {
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MachineInstr *Inst =
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B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
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.addImm(Imm.getLoBits(16).getLimitedValue());
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return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
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}
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// Lui places immediate in high 16 bits and sets low 16 bits to zero.
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if (Imm.getLoBits(16).isZero()) {
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MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
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.addImm(Imm.getHiBits(16).getLimitedValue());
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return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
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}
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// ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
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if (Imm.isSignedIntN(16)) {
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MachineInstr *Inst =
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B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
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.addImm(Imm.getLoBits(16).getLimitedValue());
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return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
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}
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// Values that cannot be materialized with single immediate instruction.
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Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
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.addImm(Imm.getHiBits(16).getLimitedValue());
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MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
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.addImm(Imm.getLoBits(16).getLimitedValue());
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if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
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return false;
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if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
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return false;
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return true;
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}
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/// When I.getOpcode() is returned, we failed to select MIPS instruction opcode.
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unsigned
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MipsInstructionSelector::selectLoadStoreOpCode(MachineInstr &I,
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MachineRegisterInfo &MRI) const {
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const Register ValueReg = I.getOperand(0).getReg();
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const LLT Ty = MRI.getType(ValueReg);
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const unsigned TySize = Ty.getSizeInBits();
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const unsigned MemSizeInBytes =
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(*I.memoperands_begin())->getSize().getValue();
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unsigned Opc = I.getOpcode();
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const bool isStore = Opc == TargetOpcode::G_STORE;
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if (isRegInGprb(ValueReg, MRI)) {
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assert(((Ty.isScalar() && TySize == 32) ||
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(Ty.isPointer() && TySize == 32 && MemSizeInBytes == 4)) &&
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"Unsupported register bank, LLT, MemSizeInBytes combination");
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(void)TySize;
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if (isStore)
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switch (MemSizeInBytes) {
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case 4:
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return Mips::SW;
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case 2:
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return Mips::SH;
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case 1:
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return Mips::SB;
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default:
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return Opc;
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}
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else
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// Unspecified extending load is selected into zeroExtending load.
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switch (MemSizeInBytes) {
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case 4:
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return Mips::LW;
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case 2:
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return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
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case 1:
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return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
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default:
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return Opc;
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}
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}
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if (isRegInFprb(ValueReg, MRI)) {
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if (Ty.isScalar()) {
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assert(((TySize == 32 && MemSizeInBytes == 4) ||
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(TySize == 64 && MemSizeInBytes == 8)) &&
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"Unsupported register bank, LLT, MemSizeInBytes combination");
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if (MemSizeInBytes == 4)
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return isStore ? Mips::SWC1 : Mips::LWC1;
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if (STI.isFP64bit())
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return isStore ? Mips::SDC164 : Mips::LDC164;
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return isStore ? Mips::SDC1 : Mips::LDC1;
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}
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if (Ty.isVector()) {
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assert(STI.hasMSA() && "Vector instructions require target with MSA.");
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assert((TySize == 128 && MemSizeInBytes == 16) &&
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"Unsupported register bank, LLT, MemSizeInBytes combination");
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switch (Ty.getElementType().getSizeInBits()) {
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case 8:
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return isStore ? Mips::ST_B : Mips::LD_B;
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case 16:
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return isStore ? Mips::ST_H : Mips::LD_H;
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case 32:
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return isStore ? Mips::ST_W : Mips::LD_W;
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case 64:
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return isStore ? Mips::ST_D : Mips::LD_D;
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default:
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return Opc;
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}
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}
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}
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return Opc;
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}
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bool MipsInstructionSelector::buildUnalignedStore(
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MachineInstr &I, unsigned Opc, MachineOperand &BaseAddr, unsigned Offset,
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MachineMemOperand *MMO) const {
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MachineInstr *NewInst =
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
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.add(I.getOperand(0))
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.add(BaseAddr)
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.addImm(Offset)
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.addMemOperand(MMO);
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if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
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return false;
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return true;
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}
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bool MipsInstructionSelector::buildUnalignedLoad(
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MachineInstr &I, unsigned Opc, Register Dest, MachineOperand &BaseAddr,
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unsigned Offset, Register TiedDest, MachineMemOperand *MMO) const {
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MachineInstr *NewInst =
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
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.addDef(Dest)
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.add(BaseAddr)
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.addImm(Offset)
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.addUse(TiedDest)
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.addMemOperand(*I.memoperands_begin());
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if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI))
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return false;
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return true;
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}
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bool MipsInstructionSelector::select(MachineInstr &I) {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (!isPreISelGenericOpcode(I.getOpcode())) {
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if (I.isCopy())
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return selectCopy(I, MRI);
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return true;
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}
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if (I.getOpcode() == Mips::G_MUL &&
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isRegInGprb(I.getOperand(0).getReg(), MRI)) {
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MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
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return false;
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Mul->getOperand(3).setIsDead(true);
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Mul->getOperand(4).setIsDead(true);
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I.eraseFromParent();
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return true;
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}
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if (selectImpl(I, *CoverageInfo))
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return true;
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MachineInstr *MI = nullptr;
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using namespace TargetOpcode;
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switch (I.getOpcode()) {
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case G_UMULH: {
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Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
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MachineInstr *PseudoMULTu, *PseudoMove;
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PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
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.addDef(PseudoMULTuReg)
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
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return false;
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PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
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.addDef(I.getOperand(0).getReg())
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.addUse(PseudoMULTuReg);
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if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_PTR_ADD: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.add(I.getOperand(2));
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break;
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}
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case G_INTTOPTR:
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case G_PTRTOINT: {
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I.setDesc(TII.get(COPY));
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return selectCopy(I, MRI);
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}
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case G_FRAME_INDEX: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
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.add(I.getOperand(0))
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.add(I.getOperand(1))
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.addImm(0);
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break;
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}
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case G_BRJT: {
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unsigned EntrySize =
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MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout());
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assert(isPowerOf2_32(EntrySize) &&
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"Non-power-of-two jump-table entry size not supported.");
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Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
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.addDef(JTIndex)
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.addUse(I.getOperand(2).getReg())
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.addImm(Log2_32(EntrySize));
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if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
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return false;
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Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
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.addDef(DestAddress)
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.addUse(I.getOperand(0).getReg())
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.addUse(JTIndex);
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if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
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return false;
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Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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MachineInstr *LW =
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
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.addDef(Dest)
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.addUse(DestAddress)
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.addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO)
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.addMemOperand(MF.getMachineMemOperand(
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MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4)));
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if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
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return false;
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if (MF.getTarget().isPositionIndependent()) {
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Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
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LW->getOperand(0).setReg(DestTmp);
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MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
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.addDef(Dest)
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.addUse(DestTmp)
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.addUse(MF.getInfo<MipsFunctionInfo>()
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->getGlobalBaseRegForGlobalISel(MF));
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if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
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return false;
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}
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MachineInstr *Branch =
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
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.addUse(Dest);
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if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
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return false;
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I.eraseFromParent();
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return true;
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}
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case G_BRINDIRECT: {
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
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.add(I.getOperand(0));
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break;
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}
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case G_PHI: {
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const Register DestReg = I.getOperand(0).getReg();
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const TargetRegisterClass *DefRC = nullptr;
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if (DestReg.isPhysical())
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DefRC = TRI.getRegClass(DestReg);
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else
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DefRC = getRegClassForTypeOnBank(DestReg, MRI);
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I.setDesc(TII.get(TargetOpcode::PHI));
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return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
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}
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case G_STORE:
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case G_LOAD:
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case G_ZEXTLOAD:
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case G_SEXTLOAD: {
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auto MMO = *I.memoperands_begin();
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MachineOperand BaseAddr = I.getOperand(1);
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int64_t SignedOffset = 0;
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// Try to fold load/store + G_PTR_ADD + G_CONSTANT
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// %SignedOffset:(s32) = G_CONSTANT i32 16_bit_signed_immediate
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// %Addr:(p0) = G_PTR_ADD %BaseAddr, %SignedOffset
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// %LoadResult/%StoreSrc = load/store %Addr(p0)
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// into:
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// %LoadResult/%StoreSrc = NewOpc %BaseAddr(p0), 16_bit_signed_immediate
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MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg());
|
|
if (Addr->getOpcode() == G_PTR_ADD) {
|
|
MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg());
|
|
if (Offset->getOpcode() == G_CONSTANT) {
|
|
APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue();
|
|
if (OffsetValue.isSignedIntN(16)) {
|
|
BaseAddr = Addr->getOperand(1);
|
|
SignedOffset = OffsetValue.getSExtValue();
|
|
}
|
|
}
|
|
}
|
|
|
|
// Unaligned memory access
|
|
if ((!MMO->getSize().hasValue() ||
|
|
MMO->getAlign() < MMO->getSize().getValue()) &&
|
|
!STI.systemSupportsUnalignedAccess()) {
|
|
if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI))
|
|
return false;
|
|
|
|
if (I.getOpcode() == G_STORE) {
|
|
if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO))
|
|
return false;
|
|
if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO))
|
|
return false;
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
if (I.getOpcode() == G_LOAD) {
|
|
Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
|
|
.addDef(ImplDef);
|
|
Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,
|
|
ImplDef, MMO))
|
|
return false;
|
|
if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(),
|
|
BaseAddr, SignedOffset, Tmp, MMO))
|
|
return false;
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
const unsigned NewOpc = selectLoadStoreOpCode(I, MRI);
|
|
if (NewOpc == I.getOpcode())
|
|
return false;
|
|
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
|
|
.add(I.getOperand(0))
|
|
.add(BaseAddr)
|
|
.addImm(SignedOffset)
|
|
.addMemOperand(MMO);
|
|
break;
|
|
}
|
|
case G_UDIV:
|
|
case G_UREM:
|
|
case G_SDIV:
|
|
case G_SREM: {
|
|
Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
|
|
bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
|
|
bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
|
|
|
|
MachineInstr *PseudoDIV, *PseudoMove;
|
|
PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(),
|
|
TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
|
|
.addDef(HILOReg)
|
|
.add(I.getOperand(1))
|
|
.add(I.getOperand(2));
|
|
if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
|
|
return false;
|
|
|
|
PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
|
|
TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addUse(HILOReg);
|
|
if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_SELECT: {
|
|
// Handle operands with pointer type.
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
|
|
.add(I.getOperand(0))
|
|
.add(I.getOperand(2))
|
|
.add(I.getOperand(1))
|
|
.add(I.getOperand(3));
|
|
break;
|
|
}
|
|
case G_UNMERGE_VALUES: {
|
|
if (I.getNumOperands() != 3)
|
|
return false;
|
|
Register Src = I.getOperand(2).getReg();
|
|
Register Lo = I.getOperand(0).getReg();
|
|
Register Hi = I.getOperand(1).getReg();
|
|
if (!isRegInFprb(Src, MRI) ||
|
|
!(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI)))
|
|
return false;
|
|
|
|
unsigned Opcode =
|
|
STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64;
|
|
|
|
MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
|
|
.addDef(Lo)
|
|
.addUse(Src)
|
|
.addImm(0);
|
|
if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI))
|
|
return false;
|
|
|
|
MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
|
|
.addDef(Hi)
|
|
.addUse(Src)
|
|
.addImm(1);
|
|
if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_IMPLICIT_DEF: {
|
|
Register Dst = I.getOperand(0).getReg();
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
|
|
.addDef(Dst);
|
|
|
|
// Set class based on register bank, there can be fpr and gpr implicit def.
|
|
MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI));
|
|
break;
|
|
}
|
|
case G_CONSTANT: {
|
|
MachineIRBuilder B(I);
|
|
if (!materialize32BitImm(I.getOperand(0).getReg(),
|
|
I.getOperand(1).getCImm()->getValue(), B))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_FCONSTANT: {
|
|
const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF();
|
|
APInt APImm = FPimm.bitcastToAPInt();
|
|
unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
|
|
|
|
if (Size == 32) {
|
|
Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
MachineIRBuilder B(I);
|
|
if (!materialize32BitImm(GPRReg, APImm, B))
|
|
return false;
|
|
|
|
MachineInstrBuilder MTC1 =
|
|
B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
|
|
if (!MTC1.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
if (Size == 64) {
|
|
Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
MachineIRBuilder B(I);
|
|
if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B))
|
|
return false;
|
|
if (!materialize32BitImm(GPRRegLow, APImm.getLoBits(32).trunc(32), B))
|
|
return false;
|
|
|
|
MachineInstrBuilder PairF64 = B.buildInstr(
|
|
STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64,
|
|
{I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh});
|
|
if (!PairF64.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_FABS: {
|
|
unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
|
|
unsigned FABSOpcode =
|
|
Size == 32 ? Mips::FABS_S
|
|
: STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
|
|
.add(I.getOperand(0))
|
|
.add(I.getOperand(1));
|
|
break;
|
|
}
|
|
case G_FPTOSI: {
|
|
unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
|
|
unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
|
|
(void)ToSize;
|
|
assert((ToSize == 32) && "Unsupported integer size for G_FPTOSI");
|
|
assert((FromSize == 32 || FromSize == 64) &&
|
|
"Unsupported floating point size for G_FPTOSI");
|
|
|
|
unsigned Opcode;
|
|
if (FromSize == 32)
|
|
Opcode = Mips::TRUNC_W_S;
|
|
else
|
|
Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
|
|
Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
|
|
MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
|
|
.addDef(ResultInFPR)
|
|
.addUse(I.getOperand(1).getReg());
|
|
if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
|
|
return false;
|
|
|
|
MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addUse(ResultInFPR);
|
|
if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_GLOBAL_VALUE: {
|
|
const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
|
|
if (MF.getTarget().isPositionIndependent()) {
|
|
MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addReg(MF.getInfo<MipsFunctionInfo>()
|
|
->getGlobalBaseRegForGlobalISel(MF))
|
|
.addGlobalAddress(GVal);
|
|
// Global Values that don't have local linkage are handled differently
|
|
// when they are part of call sequence. MipsCallLowering::lowerCall
|
|
// creates G_GLOBAL_VALUE instruction as part of call sequence and adds
|
|
// MO_GOT_CALL flag when Callee doesn't have local linkage.
|
|
if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL)
|
|
LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT_CALL);
|
|
else
|
|
LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT);
|
|
LWGOT->addMemOperand(
|
|
MF, MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF),
|
|
MachineMemOperand::MOLoad, 4, Align(4)));
|
|
if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
|
|
return false;
|
|
|
|
if (GVal->hasLocalLinkage()) {
|
|
Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
LWGOT->getOperand(0).setReg(LWGOTDef);
|
|
|
|
MachineInstr *ADDiu =
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addReg(LWGOTDef)
|
|
.addGlobalAddress(GVal);
|
|
ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
|
|
if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
} else {
|
|
Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
|
|
MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
|
|
.addDef(LUiReg)
|
|
.addGlobalAddress(GVal);
|
|
LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI);
|
|
if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
|
|
return false;
|
|
|
|
MachineInstr *ADDiu =
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addUse(LUiReg)
|
|
.addGlobalAddress(GVal);
|
|
ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
|
|
if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_JUMP_TABLE: {
|
|
if (MF.getTarget().isPositionIndependent()) {
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addReg(MF.getInfo<MipsFunctionInfo>()
|
|
->getGlobalBaseRegForGlobalISel(MF))
|
|
.addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT)
|
|
.addMemOperand(MF.getMachineMemOperand(
|
|
MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4,
|
|
Align(4)));
|
|
} else {
|
|
MI =
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI);
|
|
}
|
|
break;
|
|
}
|
|
case G_ICMP: {
|
|
struct Instr {
|
|
unsigned Opcode;
|
|
Register Def, LHS, RHS;
|
|
Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
|
|
: Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
|
|
|
|
bool hasImm() const {
|
|
if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
|
|
return true;
|
|
return false;
|
|
}
|
|
};
|
|
|
|
SmallVector<struct Instr, 2> Instructions;
|
|
Register ICMPReg = I.getOperand(0).getReg();
|
|
Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
Register LHS = I.getOperand(2).getReg();
|
|
Register RHS = I.getOperand(3).getReg();
|
|
CmpInst::Predicate Cond =
|
|
static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
|
|
|
|
switch (Cond) {
|
|
case CmpInst::ICMP_EQ: // LHS == RHS -> (LHS ^ RHS) < 1
|
|
Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
|
|
Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
|
|
break;
|
|
case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
|
|
Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
|
|
Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
|
|
break;
|
|
case CmpInst::ICMP_UGT: // LHS > RHS -> RHS < LHS
|
|
Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
|
|
break;
|
|
case CmpInst::ICMP_UGE: // LHS >= RHS -> !(LHS < RHS)
|
|
Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
|
|
Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
|
|
break;
|
|
case CmpInst::ICMP_ULT: // LHS < RHS -> LHS < RHS
|
|
Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
|
|
break;
|
|
case CmpInst::ICMP_ULE: // LHS <= RHS -> !(RHS < LHS)
|
|
Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
|
|
Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
|
|
break;
|
|
case CmpInst::ICMP_SGT: // LHS > RHS -> RHS < LHS
|
|
Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
|
|
break;
|
|
case CmpInst::ICMP_SGE: // LHS >= RHS -> !(LHS < RHS)
|
|
Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
|
|
Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
|
|
break;
|
|
case CmpInst::ICMP_SLT: // LHS < RHS -> LHS < RHS
|
|
Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
|
|
break;
|
|
case CmpInst::ICMP_SLE: // LHS <= RHS -> !(RHS < LHS)
|
|
Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
|
|
Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
MachineIRBuilder B(I);
|
|
for (const struct Instr &Instruction : Instructions) {
|
|
MachineInstrBuilder MIB = B.buildInstr(
|
|
Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
|
|
|
|
if (Instruction.hasImm())
|
|
MIB.addImm(Instruction.RHS);
|
|
else
|
|
MIB.addUse(Instruction.RHS);
|
|
|
|
if (!MIB.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_FCMP: {
|
|
unsigned MipsFCMPCondCode;
|
|
bool isLogicallyNegated;
|
|
switch (CmpInst::Predicate Cond = static_cast<CmpInst::Predicate>(
|
|
I.getOperand(1).getPredicate())) {
|
|
case CmpInst::FCMP_UNO: // Unordered
|
|
case CmpInst::FCMP_ORD: // Ordered (OR)
|
|
MipsFCMPCondCode = Mips::FCOND_UN;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_UNO;
|
|
break;
|
|
case CmpInst::FCMP_OEQ: // Equal
|
|
case CmpInst::FCMP_UNE: // Not Equal (NEQ)
|
|
MipsFCMPCondCode = Mips::FCOND_OEQ;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_OEQ;
|
|
break;
|
|
case CmpInst::FCMP_UEQ: // Unordered or Equal
|
|
case CmpInst::FCMP_ONE: // Ordered or Greater Than or Less Than (OGL)
|
|
MipsFCMPCondCode = Mips::FCOND_UEQ;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_UEQ;
|
|
break;
|
|
case CmpInst::FCMP_OLT: // Ordered or Less Than
|
|
case CmpInst::FCMP_UGE: // Unordered or Greater Than or Equal (UGE)
|
|
MipsFCMPCondCode = Mips::FCOND_OLT;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_OLT;
|
|
break;
|
|
case CmpInst::FCMP_ULT: // Unordered or Less Than
|
|
case CmpInst::FCMP_OGE: // Ordered or Greater Than or Equal (OGE)
|
|
MipsFCMPCondCode = Mips::FCOND_ULT;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_ULT;
|
|
break;
|
|
case CmpInst::FCMP_OLE: // Ordered or Less Than or Equal
|
|
case CmpInst::FCMP_UGT: // Unordered or Greater Than (UGT)
|
|
MipsFCMPCondCode = Mips::FCOND_OLE;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_OLE;
|
|
break;
|
|
case CmpInst::FCMP_ULE: // Unordered or Less Than or Equal
|
|
case CmpInst::FCMP_OGT: // Ordered or Greater Than (OGT)
|
|
MipsFCMPCondCode = Mips::FCOND_ULE;
|
|
isLogicallyNegated = Cond != CmpInst::FCMP_ULE;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
// Default compare result in gpr register will be `true`.
|
|
// We will move `false` (MIPS::Zero) to gpr result when fcmp gives false
|
|
// using MOVF_I. When orignal predicate (Cond) is logically negated
|
|
// MipsFCMPCondCode, result is inverted i.e. MOVT_I is used.
|
|
unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I;
|
|
|
|
Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
|
|
.addDef(TrueInReg)
|
|
.addUse(Mips::ZERO)
|
|
.addImm(1);
|
|
|
|
unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
|
|
unsigned FCMPOpcode =
|
|
Size == 32 ? Mips::FCMP_S32
|
|
: STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32;
|
|
MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode))
|
|
.addUse(I.getOperand(2).getReg())
|
|
.addUse(I.getOperand(3).getReg())
|
|
.addImm(MipsFCMPCondCode);
|
|
if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
|
|
return false;
|
|
|
|
MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
|
|
.addDef(I.getOperand(0).getReg())
|
|
.addUse(Mips::ZERO)
|
|
.addUse(Mips::FCC0)
|
|
.addUse(TrueInReg);
|
|
if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
case G_FENCE: {
|
|
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
|
|
break;
|
|
}
|
|
case G_VASTART: {
|
|
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
|
|
int FI = FuncInfo->getVarArgsFrameIndex();
|
|
|
|
Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
|
|
MachineInstr *LEA_ADDiu =
|
|
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
|
|
.addDef(LeaReg)
|
|
.addFrameIndex(FI)
|
|
.addImm(0);
|
|
if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
|
|
return false;
|
|
|
|
MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
|
|
.addUse(LeaReg)
|
|
.addUse(I.getOperand(0).getReg())
|
|
.addImm(0);
|
|
if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
|
|
return false;
|
|
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
I.eraseFromParent();
|
|
return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
|
|
}
|
|
|
|
namespace llvm {
|
|
InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
|
|
MipsSubtarget &Subtarget,
|
|
MipsRegisterBankInfo &RBI) {
|
|
return new MipsInstructionSelector(TM, Subtarget, RBI);
|
|
}
|
|
} // end namespace llvm
|