601e102bdb
This is part of #70452 that changes the type used for the external interface of MMO to LocationSize as opposed to uint64_t. This means the constructors take LocationSize, and convert ~UINT64_C(0) to LocationSize::beforeOrAfter(). The getSize methods return a LocationSize. This allows us to be more precise with unknown sizes, not accidentally treating them as unsigned values, and in the future should allow us to add proper scalable vector support but none of that is included in this patch. It should mostly be an NFC. Global ISel is still expected to use the underlying LLT as it needs, and are not expected to see unknown sizes for generic operations. Most of the changes are hopefully fairly mechanical, adding a lot of getValue() calls and protecting them with hasValue() where needed.
790 lines
31 KiB
C++
790 lines
31 KiB
C++
//===- PPCInstructionSelector.cpp --------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the InstructionSelector class for
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/// PowerPC.
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCMachineFunctionInfo.h"
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#include "PPCRegisterBankInfo.h"
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#include "PPCSubtarget.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/IntrinsicsPowerPC.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "ppc-gisel"
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using namespace llvm;
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namespace {
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATE_BITSET
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class PPCInstructionSelector : public InstructionSelector {
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public:
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PPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &STI,
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const PPCRegisterBankInfo &RBI);
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bool select(MachineInstr &I) override;
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static const char *getName() { return DEBUG_TYPE; }
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private:
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/// tblgen generated 'select' implementation that is used as the initial
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/// selector for the patterns that do not require complex C++.
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bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool selectFPToInt(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const;
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bool selectIntToFP(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const;
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bool selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const;
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bool selectConstantPool(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const;
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std::optional<bool> selectI64ImmDirect(MachineInstr &I,
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MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI, Register Reg,
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uint64_t Imm) const;
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bool selectI64Imm(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const;
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const PPCTargetMachine &TM;
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const PPCSubtarget &STI;
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const PPCInstrInfo &TII;
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const PPCRegisterInfo &TRI;
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const PPCRegisterBankInfo &RBI;
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#define GET_GLOBALISEL_PREDICATES_DECL
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_DECL
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#define GET_GLOBALISEL_TEMPORARIES_DECL
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_DECL
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};
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} // end anonymous namespace
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#define GET_GLOBALISEL_IMPL
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_IMPL
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PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
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const PPCSubtarget &STI,
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const PPCRegisterBankInfo &RBI)
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: TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
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RBI(RBI),
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#define GET_GLOBALISEL_PREDICATES_INIT
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_PREDICATES_INIT
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#define GET_GLOBALISEL_TEMPORARIES_INIT
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#include "PPCGenGlobalISel.inc"
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#undef GET_GLOBALISEL_TEMPORARIES_INIT
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{
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}
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static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
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if (RB->getID() == PPC::GPRRegBankID) {
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if (Ty.getSizeInBits() == 64)
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return &PPC::G8RCRegClass;
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if (Ty.getSizeInBits() <= 32)
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return &PPC::GPRCRegClass;
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}
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if (RB->getID() == PPC::FPRRegBankID) {
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if (Ty.getSizeInBits() == 32)
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return &PPC::F4RCRegClass;
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if (Ty.getSizeInBits() == 64)
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return &PPC::F8RCRegClass;
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}
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if (RB->getID() == PPC::VECRegBankID) {
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if (Ty.getSizeInBits() == 128)
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return &PPC::VSRCRegClass;
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}
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if (RB->getID() == PPC::CRRegBankID) {
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if (Ty.getSizeInBits() == 1)
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return &PPC::CRBITRCRegClass;
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if (Ty.getSizeInBits() == 4)
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return &PPC::CRRCRegClass;
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}
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llvm_unreachable("Unknown RegBank!");
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}
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static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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Register DstReg = I.getOperand(0).getReg();
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if (DstReg.isPhysical())
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return true;
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const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
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const TargetRegisterClass *DstRC =
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getRegClass(MRI.getType(DstReg), DstRegBank);
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// No need to constrain SrcReg. It will get constrained when we hit another of
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// its use or its defs.
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// Copies do not have constraints.
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if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
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<< " operand\n");
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return false;
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}
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return true;
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}
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static unsigned selectLoadStoreOp(unsigned GenericOpc, unsigned RegBankID,
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unsigned OpSize) {
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const bool IsStore = GenericOpc == TargetOpcode::G_STORE;
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switch (RegBankID) {
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case PPC::GPRRegBankID:
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switch (OpSize) {
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case 32:
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return IsStore ? PPC::STW : PPC::LWZ;
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case 64:
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return IsStore ? PPC::STD : PPC::LD;
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default:
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llvm_unreachable("Unexpected size!");
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}
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break;
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case PPC::FPRRegBankID:
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switch (OpSize) {
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case 32:
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return IsStore ? PPC::STFS : PPC::LFS;
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case 64:
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return IsStore ? PPC::STFD : PPC::LFD;
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default:
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llvm_unreachable("Unexpected size!");
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}
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break;
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default:
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llvm_unreachable("Unexpected register bank!");
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}
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return GenericOpc;
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}
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bool PPCInstructionSelector::selectIntToFP(MachineInstr &I,
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MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const {
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if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())
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return false;
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const DebugLoc &DbgLoc = I.getDebugLoc();
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const Register DstReg = I.getOperand(0).getReg();
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const Register SrcReg = I.getOperand(1).getReg();
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Register MoveReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass);
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// For now, only handle the case for 64 bit integer.
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BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg);
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bool IsSingle = MRI.getType(DstReg).getSizeInBits() == 32;
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bool IsSigned = I.getOpcode() == TargetOpcode::G_SITOFP;
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unsigned ConvOp = IsSingle ? (IsSigned ? PPC::XSCVSXDSP : PPC::XSCVUXDSP)
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: (IsSigned ? PPC::XSCVSXDDP : PPC::XSCVUXDDP);
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MachineInstr *MI =
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BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg);
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
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}
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bool PPCInstructionSelector::selectFPToInt(MachineInstr &I,
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MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const {
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if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())
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return false;
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const DebugLoc &DbgLoc = I.getDebugLoc();
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const Register DstReg = I.getOperand(0).getReg();
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const Register SrcReg = I.getOperand(1).getReg();
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Register CopyReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass);
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BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);
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Register ConvReg = MRI.createVirtualRegister(&PPC::VSFRCRegClass);
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bool IsSigned = I.getOpcode() == TargetOpcode::G_FPTOSI;
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// single-precision is stored as double-precision on PPC in registers, so
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// always use double-precision convertions.
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unsigned ConvOp = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
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BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg);
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MachineInstr *MI =
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BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg);
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
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}
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bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI) const {
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const Register DstReg = I.getOperand(0).getReg();
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const LLT DstTy = MRI.getType(DstReg);
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const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI);
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const Register SrcReg = I.getOperand(1).getReg();
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assert(DstTy.getSizeInBits() == 64 && "Unexpected dest size!");
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assert(MRI.getType(SrcReg).getSizeInBits() == 32 && "Unexpected src size!");
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Register ImpDefReg =
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MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
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ImpDefReg);
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Register NewDefReg =
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MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG),
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NewDefReg)
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.addReg(ImpDefReg)
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.addReg(SrcReg)
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.addImm(PPC::sub_32);
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MachineInstr *MI =
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BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg)
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.addReg(NewDefReg)
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.addImm(0)
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.addImm(32);
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I.eraseFromParent();
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return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
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}
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// For any 32 < Num < 64, check if the Imm contains at least Num consecutive
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// zeros and return the number of bits by the left of these consecutive zeros.
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static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
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uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm));
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uint32_t LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm));
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if ((HiTZ + LoLZ) >= Num)
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return (32 + HiTZ);
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return 0;
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}
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// Direct materialization of 64-bit constants by enumerated patterns.
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// Similar to PPCISelDAGToDAG::selectI64ImmDirect().
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std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I,
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MachineBasicBlock &MBB,
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MachineRegisterInfo &MRI,
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Register Reg,
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uint64_t Imm) const {
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unsigned TZ = llvm::countr_zero<uint64_t>(Imm);
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unsigned LZ = llvm::countl_zero<uint64_t>(Imm);
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unsigned TO = llvm::countr_one<uint64_t>(Imm);
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unsigned LO = llvm::countl_one<uint64_t>(Imm);
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uint32_t Hi32 = Hi_32(Imm);
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uint32_t Lo32 = Lo_32(Imm);
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uint32_t Shift = 0;
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// Following patterns use 1 instructions to materialize the Imm.
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// 1-1) Patterns : {zeros}{15-bit valve}
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// {ones}{15-bit valve}
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if (isInt<16>(Imm))
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg)
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.addImm(Imm)
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.constrainAllUses(TII, TRI, RBI);
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// 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}
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// {ones}{15-bit valve}{16 zeros}
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if (TZ > 15 && (LZ > 32 || LO > 32))
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg)
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.addImm((Imm >> 16) & 0xffff)
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.constrainAllUses(TII, TRI, RBI);
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// Following patterns use 2 instructions to materialize the Imm.
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assert(LZ < 64 && "Unexpected leading zeros here.");
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// Count of ones follwing the leading zeros.
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unsigned FO = llvm::countl_one<uint64_t>(Imm << LZ);
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// 2-1) Patterns : {zeros}{31-bit value}
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// {ones}{31-bit value}
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if (isInt<32>(Imm)) {
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uint64_t ImmHi16 = (Imm >> 16) & 0xffff;
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unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
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Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
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if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg)
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.addImm((Imm >> 16) & 0xffff)
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.constrainAllUses(TII, TRI, RBI))
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return false;
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Reg)
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.addReg(TmpReg, RegState::Kill)
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.addImm(Imm & 0xffff)
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.constrainAllUses(TII, TRI, RBI);
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}
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// 2-2) Patterns : {zeros}{ones}{15-bit value}{zeros}
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// {zeros}{15-bit value}{zeros}
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// {zeros}{ones}{15-bit value}
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// {ones}{15-bit value}{zeros}
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// We can take advantage of LI's sign-extension semantics to generate leading
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// ones, and then use RLDIC to mask off the ones in both sides after rotation.
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if ((LZ + FO + TZ) > 48) {
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Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
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if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
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.addImm((Imm >> TZ) & 0xffff)
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.constrainAllUses(TII, TRI, RBI))
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return false;
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg)
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.addReg(TmpReg, RegState::Kill)
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.addImm(TZ)
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.addImm(LZ)
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.constrainAllUses(TII, TRI, RBI);
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}
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// 2-3) Pattern : {zeros}{15-bit value}{ones}
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// Shift right the Imm by (48 - LZ) bits to construct a negtive 16 bits value,
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// therefore we can take advantage of LI's sign-extension semantics, and then
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// mask them off after rotation.
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//
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// +--LZ--||-15-bit-||--TO--+ +-------------|--16-bit--+
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// |00000001bbbbbbbbb1111111| -> |00000000000001bbbbbbbbb1|
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// +------------------------+ +------------------------+
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// 63 0 63 0
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// Imm (Imm >> (48 - LZ) & 0xffff)
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// +----sext-----|--16-bit--+ +clear-|-----------------+
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// |11111111111111bbbbbbbbb1| -> |00000001bbbbbbbbb1111111|
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// +------------------------+ +------------------------+
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// 63 0 63 0
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// LI8: sext many leading zeros RLDICL: rotate left (48 - LZ), clear left LZ
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if ((LZ + TO) > 48) {
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// Since the immediates with (LZ > 32) have been handled by previous
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// patterns, here we have (LZ <= 32) to make sure we will not shift right
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// the Imm by a negative value.
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assert(LZ <= 32 && "Unexpected shift value.");
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Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
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if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
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.addImm(Imm >> (48 - LZ) & 0xffff)
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.constrainAllUses(TII, TRI, RBI))
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return false;
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
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.addReg(TmpReg, RegState::Kill)
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.addImm(48 - LZ)
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.addImm(LZ)
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.constrainAllUses(TII, TRI, RBI);
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}
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// 2-4) Patterns : {zeros}{ones}{15-bit value}{ones}
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// {ones}{15-bit value}{ones}
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// We can take advantage of LI's sign-extension semantics to generate leading
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// ones, and then use RLDICL to mask off the ones in left sides (if required)
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// after rotation.
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//
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// +-LZ-FO||-15-bit-||--TO--+ +-------------|--16-bit--+
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// |00011110bbbbbbbbb1111111| -> |000000000011110bbbbbbbbb|
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// +------------------------+ +------------------------+
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// 63 0 63 0
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// Imm (Imm >> TO) & 0xffff
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// +----sext-----|--16-bit--+ +LZ|---------------------+
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// |111111111111110bbbbbbbbb| -> |00011110bbbbbbbbb1111111|
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// +------------------------+ +------------------------+
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// 63 0 63 0
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// LI8: sext many leading zeros RLDICL: rotate left TO, clear left LZ
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if ((LZ + FO + TO) > 48) {
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Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
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if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
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.addImm((Imm >> TO) & 0xffff)
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.constrainAllUses(TII, TRI, RBI))
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return false;
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return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
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.addReg(TmpReg, RegState::Kill)
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.addImm(TO)
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.addImm(LZ)
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.constrainAllUses(TII, TRI, RBI);
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}
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// 2-5) Pattern : {32 zeros}{****}{0}{15-bit value}
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// If Hi32 is zero and the Lo16(in Lo32) can be presented as a positive 16 bit
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// value, we can use LI for Lo16 without generating leading ones then add the
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// Hi16(in Lo32).
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if (LZ == 32 && ((Lo32 & 0x8000) == 0)) {
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Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
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if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
|
|
.addImm(Lo32 & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(Lo32 >> 16)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
// 2-6) Patterns : {******}{49 zeros}{******}
|
|
// {******}{49 ones}{******}
|
|
// If the Imm contains 49 consecutive zeros/ones, it means that a total of 15
|
|
// bits remain on both sides. Rotate right the Imm to construct an int<16>
|
|
// value, use LI for int<16> value and then use RLDICL without mask to rotate
|
|
// it back.
|
|
//
|
|
// 1) findContiguousZerosAtLeast(Imm, 49)
|
|
// +------|--zeros-|------+ +---ones--||---15 bit--+
|
|
// |bbbbbb0000000000aaaaaa| -> |0000000000aaaaaabbbbbb|
|
|
// +----------------------+ +----------------------+
|
|
// 63 0 63 0
|
|
//
|
|
// 2) findContiguousZerosAtLeast(~Imm, 49)
|
|
// +------|--ones--|------+ +---ones--||---15 bit--+
|
|
// |bbbbbb1111111111aaaaaa| -> |1111111111aaaaaabbbbbb|
|
|
// +----------------------+ +----------------------+
|
|
// 63 0 63 0
|
|
if ((Shift = findContiguousZerosAtLeast(Imm, 49)) ||
|
|
(Shift = findContiguousZerosAtLeast(~Imm, 49))) {
|
|
uint64_t RotImm = APInt(64, Imm).rotr(Shift).getZExtValue();
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg)
|
|
.addImm(RotImm & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(Shift)
|
|
.addImm(0)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
|
|
// Following patterns use 3 instructions to materialize the Imm.
|
|
|
|
// 3-1) Patterns : {zeros}{ones}{31-bit value}{zeros}
|
|
// {zeros}{31-bit value}{zeros}
|
|
// {zeros}{ones}{31-bit value}
|
|
// {ones}{31-bit value}{zeros}
|
|
// We can take advantage of LIS's sign-extension semantics to generate leading
|
|
// ones, add the remaining bits with ORI, and then use RLDIC to mask off the
|
|
// ones in both sides after rotation.
|
|
if ((LZ + FO + TZ) > 32) {
|
|
uint64_t ImmHi16 = (Imm >> (TZ + 16)) & 0xffff;
|
|
unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg)
|
|
.addImm(ImmHi16)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm((Imm >> TZ) & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addImm(TZ)
|
|
.addImm(LZ)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
// 3-2) Pattern : {zeros}{31-bit value}{ones}
|
|
// Shift right the Imm by (32 - LZ) bits to construct a negative 32 bits
|
|
// value, therefore we can take advantage of LIS's sign-extension semantics,
|
|
// add the remaining bits with ORI, and then mask them off after rotation.
|
|
// This is similar to Pattern 2-3, please refer to the diagram there.
|
|
if ((LZ + TO) > 32) {
|
|
// Since the immediates with (LZ > 32) have been handled by previous
|
|
// patterns, here we have (LZ <= 32) to make sure we will not shift right
|
|
// the Imm by a negative value.
|
|
assert(LZ <= 32 && "Unexpected shift value.");
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg)
|
|
.addImm((Imm >> (48 - LZ)) & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm((Imm >> (32 - LZ)) & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addImm(32 - LZ)
|
|
.addImm(LZ)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
// 3-3) Patterns : {zeros}{ones}{31-bit value}{ones}
|
|
// {ones}{31-bit value}{ones}
|
|
// We can take advantage of LIS's sign-extension semantics to generate leading
|
|
// ones, add the remaining bits with ORI, and then use RLDICL to mask off the
|
|
// ones in left sides (if required) after rotation.
|
|
// This is similar to Pattern 2-4, please refer to the diagram there.
|
|
if ((LZ + FO + TO) > 32) {
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg)
|
|
.addImm((Imm >> (TO + 16)) & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm((Imm >> TO) & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addImm(TO)
|
|
.addImm(LZ)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
// 3-4) Patterns : High word == Low word
|
|
if (Hi32 == Lo32) {
|
|
// Handle the first 32 bits.
|
|
uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;
|
|
unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg)
|
|
.addImm(ImmHi16)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(Lo32 & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIMI), Reg)
|
|
.addReg(Tmp2Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addImm(32)
|
|
.addImm(0)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
// 3-5) Patterns : {******}{33 zeros}{******}
|
|
// {******}{33 ones}{******}
|
|
// If the Imm contains 33 consecutive zeros/ones, it means that a total of 31
|
|
// bits remain on both sides. Rotate right the Imm to construct an int<32>
|
|
// value, use LIS + ORI for int<32> value and then use RLDICL without mask to
|
|
// rotate it back.
|
|
// This is similar to Pattern 2-6, please refer to the diagram there.
|
|
if ((Shift = findContiguousZerosAtLeast(Imm, 33)) ||
|
|
(Shift = findContiguousZerosAtLeast(~Imm, 33))) {
|
|
uint64_t RotImm = APInt(64, Imm).rotr(Shift).getZExtValue();
|
|
uint64_t ImmHi16 = (RotImm >> 16) & 0xffff;
|
|
unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
|
|
Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg)
|
|
.addImm(ImmHi16)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(RotImm & 0xffff)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg)
|
|
.addReg(Tmp2Reg, RegState::Kill)
|
|
.addImm(Shift)
|
|
.addImm(0)
|
|
.constrainAllUses(TII, TRI, RBI);
|
|
}
|
|
|
|
// If we end up here then no instructions were inserted.
|
|
return std::nullopt;
|
|
}
|
|
|
|
// Derived from PPCISelDAGToDAG::selectI64Imm().
|
|
// TODO: Add support for prefixed instructions.
|
|
bool PPCInstructionSelector::selectI64Imm(MachineInstr &I,
|
|
MachineBasicBlock &MBB,
|
|
MachineRegisterInfo &MRI) const {
|
|
assert(I.getOpcode() == TargetOpcode::G_CONSTANT && "Unexpected G code");
|
|
|
|
Register DstReg = I.getOperand(0).getReg();
|
|
int64_t Imm = I.getOperand(1).getCImm()->getValue().getZExtValue();
|
|
// No more than 3 instructions are used if we can select the i64 immediate
|
|
// directly.
|
|
if (std::optional<bool> Res = selectI64ImmDirect(I, MBB, MRI, DstReg, Imm)) {
|
|
I.eraseFromParent();
|
|
return *Res;
|
|
}
|
|
|
|
// Calculate the last bits as required.
|
|
uint32_t Hi16 = (Lo_32(Imm) >> 16) & 0xffff;
|
|
uint32_t Lo16 = Lo_32(Imm) & 0xffff;
|
|
|
|
Register Reg =
|
|
(Hi16 || Lo16) ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
|
|
|
|
// Handle the upper 32 bit value.
|
|
std::optional<bool> Res =
|
|
selectI64ImmDirect(I, MBB, MRI, Reg, Imm & 0xffffffff00000000);
|
|
if (!Res || !*Res)
|
|
return false;
|
|
|
|
// Add in the last bits as required.
|
|
if (Hi16) {
|
|
Register TmpReg =
|
|
Lo16 ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), TmpReg)
|
|
.addReg(Reg, RegState::Kill)
|
|
.addImm(Hi16)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
Reg = TmpReg;
|
|
}
|
|
if (Lo16) {
|
|
if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg)
|
|
.addReg(Reg, RegState::Kill)
|
|
.addImm(Lo16)
|
|
.constrainAllUses(TII, TRI, RBI))
|
|
return false;
|
|
}
|
|
I.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool PPCInstructionSelector::selectConstantPool(
|
|
MachineInstr &I, MachineBasicBlock &MBB, MachineRegisterInfo &MRI) const {
|
|
const DebugLoc &DbgLoc = I.getDebugLoc();
|
|
MachineFunction *MF = MBB.getParent();
|
|
|
|
// TODO: handle 32-bit.
|
|
// TODO: Enabling floating point constant pool selection on AIX requires
|
|
// global isel on big endian target enabled first.
|
|
// See CallLowering::enableBigEndian().
|
|
if (!STI.isPPC64() || !STI.isLittleEndian())
|
|
return false;
|
|
|
|
MF->getInfo<PPCFunctionInfo>()->setUsesTOCBasePtr();
|
|
|
|
const Register DstReg = I.getOperand(0).getReg();
|
|
unsigned CPI = I.getOperand(1).getIndex();
|
|
|
|
// Address stored in the TOC entry. This is related to code model and the ABI
|
|
// we are currently using. For now we only handle 64-bit Linux LE. PowerPC
|
|
// only supports small, medium and large code model.
|
|
const CodeModel::Model CModel = TM.getCodeModel();
|
|
assert(!(CModel == CodeModel::Tiny || CModel == CodeModel::Kernel) &&
|
|
"PowerPC doesn't support tiny or kernel code models.");
|
|
|
|
const MCRegister TOCReg = STI.getTOCPointerRegister();
|
|
MachineMemOperand *MMO = MF->getMachineMemOperand(
|
|
MachinePointerInfo::getGOT(*MF), MachineMemOperand::MOLoad,
|
|
MRI.getType(DstReg), MF->getDataLayout().getPointerABIAlignment(0));
|
|
|
|
MachineInstr *MI = nullptr;
|
|
// For now we only handle 64-bit Linux.
|
|
if (CModel == CodeModel::Small) {
|
|
// For small code model, generate LDtocCPT(CPI, X2).
|
|
MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocCPT), DstReg)
|
|
.addConstantPoolIndex(CPI)
|
|
.addReg(TOCReg)
|
|
.addMemOperand(MMO);
|
|
} else {
|
|
Register HaAddrReg = MRI.createVirtualRegister(&PPC::G8RCRegClass);
|
|
BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDIStocHA8), HaAddrReg)
|
|
.addReg(TOCReg)
|
|
.addConstantPoolIndex(CPI);
|
|
|
|
if (CModel == CodeModel::Large)
|
|
// For large code model, generate LDtocL(CPI, ADDIStocHA8(X2, CPI))
|
|
MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::LDtocL), DstReg)
|
|
.addConstantPoolIndex(CPI)
|
|
.addReg(HaAddrReg)
|
|
.addMemOperand(MMO);
|
|
else
|
|
// For medium code model, generate ADDItocL8(CPI, ADDIStocHA8(X2, CPI))
|
|
MI = BuildMI(MBB, I, DbgLoc, TII.get(PPC::ADDItocL8), DstReg)
|
|
.addReg(HaAddrReg)
|
|
.addConstantPoolIndex(CPI);
|
|
}
|
|
|
|
I.eraseFromParent();
|
|
return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
|
|
}
|
|
|
|
bool PPCInstructionSelector::select(MachineInstr &I) {
|
|
auto &MBB = *I.getParent();
|
|
auto &MF = *MBB.getParent();
|
|
auto &MRI = MF.getRegInfo();
|
|
|
|
if (!isPreISelGenericOpcode(I.getOpcode())) {
|
|
if (I.isCopy())
|
|
return selectCopy(I, TII, MRI, TRI, RBI);
|
|
|
|
return true;
|
|
}
|
|
|
|
if (selectImpl(I, *CoverageInfo))
|
|
return true;
|
|
|
|
unsigned Opcode = I.getOpcode();
|
|
|
|
switch (Opcode) {
|
|
default:
|
|
return false;
|
|
case TargetOpcode::G_LOAD:
|
|
case TargetOpcode::G_STORE: {
|
|
GLoadStore &LdSt = cast<GLoadStore>(I);
|
|
LLT PtrTy = MRI.getType(LdSt.getPointerReg());
|
|
|
|
if (PtrTy != LLT::pointer(0, 64)) {
|
|
LLVM_DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
|
|
<< ", expected: " << LLT::pointer(0, 64) << '\n');
|
|
return false;
|
|
}
|
|
|
|
auto SelectLoadStoreAddressingMode = [&]() -> MachineInstr * {
|
|
const unsigned NewOpc = selectLoadStoreOp(
|
|
I.getOpcode(), RBI.getRegBank(LdSt.getReg(0), MRI, TRI)->getID(),
|
|
LdSt.getMemSizeInBits().getValue());
|
|
|
|
if (NewOpc == I.getOpcode())
|
|
return nullptr;
|
|
|
|
// For now, simply use DForm with load/store addr as base and 0 as imm.
|
|
// FIXME: optimize load/store with some specific address patterns.
|
|
I.setDesc(TII.get(NewOpc));
|
|
Register AddrReg = I.getOperand(1).getReg();
|
|
bool IsKill = I.getOperand(1).isKill();
|
|
I.getOperand(1).ChangeToImmediate(0);
|
|
I.addOperand(*I.getParent()->getParent(),
|
|
MachineOperand::CreateReg(AddrReg, /* isDef */ false,
|
|
/* isImp */ false, IsKill));
|
|
return &I;
|
|
};
|
|
|
|
MachineInstr *LoadStore = SelectLoadStoreAddressingMode();
|
|
if (!LoadStore)
|
|
return false;
|
|
|
|
return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI);
|
|
}
|
|
case TargetOpcode::G_SITOFP:
|
|
case TargetOpcode::G_UITOFP:
|
|
return selectIntToFP(I, MBB, MRI);
|
|
case TargetOpcode::G_FPTOSI:
|
|
case TargetOpcode::G_FPTOUI:
|
|
return selectFPToInt(I, MBB, MRI);
|
|
// G_SEXT will be selected in tb-gen pattern.
|
|
case TargetOpcode::G_ZEXT:
|
|
return selectZExt(I, MBB, MRI);
|
|
case TargetOpcode::G_CONSTANT:
|
|
return selectI64Imm(I, MBB, MRI);
|
|
case TargetOpcode::G_CONSTANT_POOL:
|
|
return selectConstantPool(I, MBB, MRI);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
namespace llvm {
|
|
InstructionSelector *
|
|
createPPCInstructionSelector(const PPCTargetMachine &TM,
|
|
const PPCSubtarget &Subtarget,
|
|
const PPCRegisterBankInfo &RBI) {
|
|
return new PPCInstructionSelector(TM, Subtarget, RBI);
|
|
}
|
|
} // end namespace llvm
|