Craig Topper 852eb20b4f [RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593) ...

This is inspired by AArch64's getSameKindOfOperandsMapping, but based on
what RISC-V currently needs.

This removes the special vector case for G_ADD/SUB and unifies integer
and FP operations into the same handler.

G_SEXTLOAD/ZEXTLOAD have been separated from integer since they should
only be scalar integer and never vector.

2024-04-04 16:17:19 -07:00

..

RISCVCallLowering.cpp

[RISCV] RISCV vector calling convention (2/2) (#79096)

2024-03-30 21:05:33 +08:00

RISCVCallLowering.h

[RISCV][GISEL] lowerFormalArguments for variadic arguments (#73064)

2023-11-30 12:15:35 -05:00

RISCVInstructionSelector.cpp

[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)

2024-03-23 13:12:44 +01:00

RISCVLegalizerInfo.cpp

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVLegalizerInfo.h

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVO0PreLegalizerCombiner.cpp

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RISCVPostLegalizerCombiner.cpp

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RISCVPreLegalizerCombiner.cpp

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RISCVRegisterBankInfo.cpp

[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593)

2024-04-04 16:17:19 -07:00

RISCVRegisterBankInfo.h

[RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)

2023-11-30 11:38:02 -05:00

RISCVRegisterBanks.td

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