e64e15ee59
Registers shouldn't depend on the scheduler, but a scheduler predicate could depend on a register. This would make it possible to move VLDSX0Pred out of the SiFive7 scheduler model to RISCVSchedule.td if another model needed it.
79 lines
2.7 KiB
TableGen
79 lines
2.7 KiB
TableGen
//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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include "RISCVFeatures.td"
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//===----------------------------------------------------------------------===//
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// Named operands for CSR instructions.
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//===----------------------------------------------------------------------===//
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include "RISCVSystemOperands.td"
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//===----------------------------------------------------------------------===//
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// Registers, calling conventions, instruction descriptions.
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//===----------------------------------------------------------------------===//
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include "RISCVRegisterInfo.td"
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include "RISCVSchedule.td"
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include "RISCVCallingConv.td"
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include "RISCVInstrInfo.td"
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include "GISel/RISCVRegisterBanks.td"
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//===----------------------------------------------------------------------===//
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// RISC-V macro fusions.
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//===----------------------------------------------------------------------===//
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include "RISCVMacroFusion.td"
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//===----------------------------------------------------------------------===//
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// RISC-V Scheduling Models
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//===----------------------------------------------------------------------===//
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include "RISCVSchedRocket.td"
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include "RISCVSchedSiFive7.td"
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include "RISCVSchedSiFiveP400.td"
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include "RISCVSchedSiFiveP600.td"
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include "RISCVSchedSyntacoreSCR1.td"
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include "RISCVSchedXiangShanNanHu.td"
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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include "RISCVProcessors.td"
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//===----------------------------------------------------------------------===//
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// Define the RISC-V target.
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//===----------------------------------------------------------------------===//
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def RISCVInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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}
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def RISCVAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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let AllowDuplicateRegisterNames = 1;
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}
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def RISCVAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def RISCV : Target {
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let InstructionSet = RISCVInstrInfo;
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let AssemblyParsers = [RISCVAsmParser];
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let AssemblyWriters = [RISCVAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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