24bb36e58e
Most places assign Opcode right after assigning every other bit in
Inst. I don't think treating Opcode separately adds much value. It
doesn't hide what bits belong to the opcode since every other bits is
listed.
This makes RVInst consistent with RVInst16 subclasss which already
assign Inst{1-0} directly.
Reviewed By: asb, wangpc
Differential Revision: https://reviews.llvm.org/D155797
333 lines
8.5 KiB
TableGen
333 lines
8.5 KiB
TableGen
//===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V V extension instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class RISCVVFormat<bits<3> val> {
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bits<3> Value = val;
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}
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def OPIVV : RISCVVFormat<0b000>;
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def OPFVV : RISCVVFormat<0b001>;
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def OPMVV : RISCVVFormat<0b010>;
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def OPIVI : RISCVVFormat<0b011>;
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def OPIVX : RISCVVFormat<0b100>;
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def OPFVF : RISCVVFormat<0b101>;
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def OPMVX : RISCVVFormat<0b110>;
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def OPCFG : RISCVVFormat<0b111>;
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class RISCVMOP<bits<2> val> {
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bits<2> Value = val;
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}
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def MOPLDUnitStride : RISCVMOP<0b00>;
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def MOPLDIndexedUnord : RISCVMOP<0b01>;
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def MOPLDStrided : RISCVMOP<0b10>;
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def MOPLDIndexedOrder : RISCVMOP<0b11>;
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def MOPSTUnitStride : RISCVMOP<0b00>;
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def MOPSTIndexedUnord : RISCVMOP<0b01>;
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def MOPSTStrided : RISCVMOP<0b10>;
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def MOPSTIndexedOrder : RISCVMOP<0b11>;
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class RISCVLSUMOP<bits<5> val> {
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bits<5> Value = val;
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}
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def LUMOPUnitStride : RISCVLSUMOP<0b00000>;
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def LUMOPUnitStrideMask : RISCVLSUMOP<0b01011>;
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def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
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def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
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def SUMOPUnitStride : RISCVLSUMOP<0b00000>;
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def SUMOPUnitStrideMask : RISCVLSUMOP<0b01011>;
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def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
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class RISCVWidth<bits<4> val> {
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bits<4> Value = val;
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}
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def LSWidth8 : RISCVWidth<0b0000>;
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def LSWidth16 : RISCVWidth<0b0101>;
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def LSWidth32 : RISCVWidth<0b0110>;
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def LSWidth64 : RISCVWidth<0b0111>;
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class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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bits<5> uimm;
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bits<5> rd;
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bits<10> vtypei;
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let Inst{31} = 1;
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let Inst{30} = 1;
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let Inst{29-20} = vtypei{9-0};
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let Inst{19-15} = uimm;
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let Inst{14-12} = OPCFG.Value;
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let Inst{11-7} = rd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Defs = [VTYPE, VL];
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}
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class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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bits<5> rs1;
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bits<5> rd;
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bits<11> vtypei;
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let Inst{31} = 0;
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let Inst{30-20} = vtypei;
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let Inst{19-15} = rs1;
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let Inst{14-12} = OPCFG.Value;
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let Inst{11-7} = rd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Defs = [VTYPE, VL];
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}
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class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31} = 1;
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let Inst{30-25} = 0b000000;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = OPCFG.Value;
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let Inst{11-7} = rd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Defs = [VTYPE, VL];
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}
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class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> vs1;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = vs1;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> imm;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = imm;
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let Inst{14-12} = OPIVI.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
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dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> vd;
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bit vm;
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let Inst{31-26} = funct6;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = vs1;
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let Inst{14-12} = opv.Value;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_OP_V.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
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bits<3> width, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = MOPLDUnitStride.Value;
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let Inst{25} = vm;
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let Inst{24-20} = lumop.Value;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_LOAD_FP.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = MOPLDStrided.Value;
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let Inst{25} = vm;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_LOAD_FP.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> rs1;
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bits<5> vd;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = mop.Value;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_LOAD_FP.Value;
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let Uses = [VTYPE, VL];
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let RVVConstraint = VMConstraint;
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}
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class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
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bits<3> width, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs1;
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bits<5> vs3;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = MOPSTUnitStride.Value;
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let Inst{25} = vm;
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let Inst{24-20} = sumop.Value;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vs3;
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let Inst{6-0} = OPC_STORE_FP.Value;
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let Uses = [VTYPE, VL];
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}
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class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> vs3;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = MOPSTStrided.Value;
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let Inst{25} = vm;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vs3;
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let Inst{6-0} = OPC_STORE_FP.Value;
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let Uses = [VTYPE, VL];
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}
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class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> vs2;
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bits<5> rs1;
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bits<5> vs3;
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bit vm;
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let Inst{31-29} = nf;
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let Inst{28} = mew;
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let Inst{27-26} = mop.Value;
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let Inst{25} = vm;
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let Inst{24-20} = vs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = width;
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let Inst{11-7} = vs3;
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let Inst{6-0} = OPC_STORE_FP.Value;
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let Uses = [VTYPE, VL];
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}
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