3544d200d9
The patch adds the regularization pass that prepare LLVM IR for the IR translation. It also contains following changes: - reduce indentation, make getNonParametrizedType, getSamplerType, getPipeType, getImageType, getSampledImageType static in SPIRVBuiltins, - rename mayBeOclOrSpirvBuiltin to getOclOrSpirvBuiltinDemangledName, - move isOpenCLBuiltinType, isSPIRVBuiltinType, isSpecialType from SPIRVGlobalRegistry.cpp to SPIRVUtils.cpp, renaming isSpecialType to isSpecialOpaqueType, - implment getTgtMemIntrinsic() in SPIRVISelLowering, - add hasSideEffects = 0 in Pseudo (SPIRVInstrFormats.td), - add legalization rule for G_MEMSET, correct G_BRCOND rule, - add capability processing for OpBuildNDRange in SPIRVModuleAnalysis, - don't correct types of registers holding constants and used in G_ADDRSPACE_CAST (SPIRVPreLegalizer.cpp), - lower memset/bswap intrinsics to functions in SPIRVPrepareFunctions, - change TargetLoweringObjectFileELF to SPIRVTargetObjectFile in SPIRVTargetMachine.cpp, - correct comments. 5 LIT tests are added to show the improvement. Differential Revision: https://reviews.llvm.org/D133253 Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
33 lines
886 B
TableGen
33 lines
886 B
TableGen
//===-- SPIRVInstrFormats.td - SPIR-V Instruction Formats --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def StringImm: Operand<i32>{
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let PrintMethod="printStringImm";
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}
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class Op<bits<16> Opcode, dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: Instruction {
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field bits<16> Inst;
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let Inst = Opcode;
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let Namespace = "SPIRV";
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let DecoderNamespace = "SPIRV";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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// Pseudo instructions
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class Pseudo<dag outs, dag ins> : Op<0, outs, ins, ""> {
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let isPseudo = 1;
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let hasSideEffects = 0;
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}
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