1ca8092e87
APX assembly syntax recommendations: https://cdrdv2.intel.com/v1/dl/getContent/817241 NOTE: The change in llvm/tools/llvm-exegesis/lib/X86/Target.cpp is for test LLVM :: tools/llvm-exegesis/X86/latency/latency-SETCCr-cond-codes-sweep.s For `SETcc`, llvm-exegesis would randomly choose 1 other instruction to test with `SETcc`, after selecting the instruction, llvm-exegesis would check if the operand is initialized and valid, if not `randomizeTargetMCOperand` would choose a value for invalid operand, it misses support for condition code operand, which cause the flaky failure after `CCMP` supported. llvm-exegesis can choose `CCMP` without specifying ccmp feature b/c it use `MCSubtarget` and only16/32/64 bit is considered. llvm-exegesis doesn't choose other instructions b/c requirement in `hasAliasingRegistersThrough`: the instruction should use GPR (defined by `SETcc`) and define `EFLAGS` (used by `SETcc`).
111 lines
4.8 KiB
TableGen
111 lines
4.8 KiB
TableGen
//===-- X86InstrConditionalCompare.td - Conditional Compare --*- tablegen -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 conditional compare instructions.
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//
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//===----------------------------------------------------------------------===//
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class BinCondOp<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2, string m>
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: ITy<o, f, t, (outs), (ins op1:$src1, op2:$src2, cflags:$dcf, ccode:$cond),
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m#"${cond}", "$dcf\t{$src2, $src1|$src1, $src2}" , []>, T_MAP4, EVEX, Requires<[In64BitMode]> {
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let isCodeGenOnly = 1;
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let ForceDisassemble = 1;
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let Uses = [EFLAGS];
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let Defs = [EFLAGS];
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let hasTwoConditionalOps = 1;
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let ImmT = !if(!eq(op2, i16i8imm), Imm8,
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!if(!eq(op2, i32i8imm), Imm8,
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!if(!eq(op2, i64i8imm), Imm8,
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!if(!eq(op2, i8imm), Imm8,
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!if(!eq(op2, i16imm), Imm16,
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!if(!eq(op2, i32imm), Imm32,
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!if(!eq(op2, i64i32imm), Imm32S, NoImm)))))));
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}
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class Ccmp<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>:
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BinCondOp<o, f, t, op1, op2, "ccmp">;
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class Ctest<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>:
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BinCondOp<o, f, t, op1, op2, "ctest">;
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//===----------------------------------------------------------------------===//
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// CCMP Instructions
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//
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let SchedRW = [WriteALU] in {
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def CCMP8rr : Ccmp<0x38, MRMDestReg, Xi8, GR8, GR8>;
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def CCMP16rr: Ccmp<0x39, MRMDestReg, Xi16, GR16, GR16>, PD;
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def CCMP32rr: Ccmp<0x39, MRMDestReg, Xi32, GR32, GR32>;
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def CCMP64rr: Ccmp<0x39, MRMDestReg, Xi64, GR64, GR64>;
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def CCMP8rr_REV : Ccmp<0x3a, MRMSrcReg, Xi8, GR8, GR8>;
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def CCMP16rr_REV: Ccmp<0x3b, MRMSrcReg, Xi16, GR16, GR16>, PD;
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def CCMP32rr_REV: Ccmp<0x3b, MRMSrcReg, Xi32, GR32, GR32>;
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def CCMP64rr_REV: Ccmp<0x3b, MRMSrcReg, Xi64, GR64, GR64>;
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def CCMP16ri8: Ccmp<0x83, MRM7r, Xi16, GR16, i16i8imm>, PD;
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def CCMP32ri8: Ccmp<0x83, MRM7r, Xi32, GR32, i32i8imm>;
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def CCMP64ri8: Ccmp<0x83, MRM7r, Xi64, GR64, i64i8imm>;
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def CCMP8ri : Ccmp<0x80, MRM7r, Xi8, GR8, i8imm>;
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def CCMP16ri: Ccmp<0x81, MRM7r, Xi16, GR16, i16imm>, PD;
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def CCMP32ri: Ccmp<0x81, MRM7r, Xi32, GR32, i32imm>;
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def CCMP64ri32: Ccmp<0x81, MRM7r, Xi64, GR64, i64i32imm>;
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}
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let mayLoad = 1 in {
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let SchedRW = [WriteALU.Folded] in {
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def CCMP16mi8: Ccmp<0x83, MRM7m, Xi16, i16mem, i16i8imm>, PD;
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def CCMP32mi8: Ccmp<0x83, MRM7m, Xi32, i32mem, i32i8imm>;
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def CCMP64mi8: Ccmp<0x83, MRM7m, Xi64, i64mem, i64i8imm>;
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def CCMP8mi : Ccmp<0x80, MRM7m, Xi8, i8mem, i8imm>;
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def CCMP16mi: Ccmp<0x81, MRM7m, Xi16, i16mem, i16imm>, PD;
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def CCMP32mi: Ccmp<0x81, MRM7m, Xi32, i32mem, i32imm>;
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def CCMP64mi32: Ccmp<0x81, MRM7m, Xi64, i64mem, i64i32imm>;
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}
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let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold] in {
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def CCMP8rm : Ccmp<0x3a, MRMSrcMem, Xi8, GR8, i8mem>;
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def CCMP16rm: Ccmp<0x3b, MRMSrcMem, Xi16, GR16, i16mem>, PD;
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def CCMP32rm: Ccmp<0x3b, MRMSrcMem, Xi32, GR32, i32mem>;
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def CCMP64rm: Ccmp<0x3b, MRMSrcMem, Xi64, GR64, i64mem>;
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def CCMP8mr : Ccmp<0x38, MRMDestMem, Xi8, i8mem, GR8>;
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def CCMP16mr: Ccmp<0x39, MRMDestMem, Xi16, i16mem, GR16>, PD;
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def CCMP32mr: Ccmp<0x39, MRMDestMem, Xi32, i32mem, GR32>;
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def CCMP64mr: Ccmp<0x39, MRMDestMem, Xi64, i64mem, GR64>;
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}
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}
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//===----------------------------------------------------------------------===//
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// CTEST Instructions
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//
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let SchedRW = [WriteALU] in {
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let isCommutable = 1 in {
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def CTEST8rr : Ctest<0x84, MRMDestReg, Xi8, GR8, GR8>;
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def CTEST16rr: Ctest<0x85, MRMDestReg, Xi16, GR16, GR16>, PD;
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def CTEST32rr: Ctest<0x85, MRMDestReg, Xi32, GR32, GR32>;
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def CTEST64rr: Ctest<0x85, MRMDestReg, Xi64, GR64, GR64>;
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}
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def CTEST8ri : Ctest<0xF6, MRM0r, Xi8, GR8, i8imm>;
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def CTEST16ri: Ctest<0xF7, MRM0r, Xi16, GR16, i16imm>, PD;
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def CTEST32ri: Ctest<0xF7, MRM0r, Xi32, GR32, i32imm>;
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def CTEST64ri32: Ctest<0xF7, MRM0r, Xi64, GR64, i64i32imm>;
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}
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let mayLoad = 1 in {
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let SchedRW = [WriteALU.Folded] in {
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def CTEST8mi : Ctest<0xF6, MRM0m, Xi8, i8mem, i8imm>;
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def CTEST16mi: Ctest<0xF7, MRM0m, Xi16, i16mem, i16imm>, PD;
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def CTEST32mi: Ctest<0xF7, MRM0m, Xi32, i32mem, i32imm>;
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def CTEST64mi32: Ctest<0xF7, MRM0m, Xi64, i64mem, i64i32imm>;
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}
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let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold] in {
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def CTEST8mr : Ctest<0x84, MRMDestMem, Xi8, i8mem, GR8>;
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def CTEST16mr: Ctest<0x85, MRMDestMem, Xi16, i16mem, GR16>, PD;
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def CTEST32mr: Ctest<0x85, MRMDestMem, Xi32, i32mem, GR32>;
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def CTEST64mr: Ctest<0x85, MRMDestMem, Xi64, i64mem, GR64>;
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}
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}
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