2a859b2014
The cost of vector instructions has always been high under AArch64, in order to add a high cost for inserts/extracts, shuffles and scalarization. This is a conservative approach to limit the scope of unusual SLP vectorization where the codegen ends up being quite poor, but has always been higher than the correct costs would be for any specific core. This relaxes that, reducing the vector insert/extract cost from 3 to 2. It is a generalization of D142359 to all AArch64 cpus. The ScalarizationOverhead is also overridden for integer vector at the same time, to remove the effect of lane 0 being considered free for integer vectors (something that should only be true for float when scalarizing). The lower insert/extract cost will reduce the cost of insert, extracts, shuffling and scalarization. The adjustments of ScalaizationOverhead will increase the cost on integer, especially for small vectors. The end result will be lower cost for float and long-integer types, some higher cost for some smaller vectors. This, along with the raw insert/extract cost being lower, will generally mean more vectorization from the Loop and SLP vectorizer. We may end up regretting this, as that vectorization is not always profitable. In all the benchmarking I have done this is generally an improvement in the overall performance, and I've attempted to address the places where it wasn't with other costmodel adjustments. Differential Revision: https://reviews.llvm.org/D155459
282 lines
13 KiB
LLVM
282 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes="print<cost-model>" -disable-output -mtriple=arm64-apple-ios < %s 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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define i8 @fshr_i8_3rd_arg_const(i8 %a, i8 %b) {
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; CHECK-LABEL: 'fshr_i8_3rd_arg_const'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fshr = tail call i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i8 %fshr
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;
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entry:
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%fshr = tail call i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 9)
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ret i8 %fshr
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}
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define i8 @fshr_i8_3rd_arg_var(i8 %a, i8 %b, i8 %c) {
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; CHECK-LABEL: 'fshr_i8_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %fshr = tail call i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i8 %fshr
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;
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entry:
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%fshr = tail call i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 %c)
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ret i8 %fshr
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}
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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define i16 @fshr_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: 'fshr_i16'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fshr = tail call i16 @llvm.fshr.i16(i16 %a, i16 %b, i16 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i16 %fshr
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;
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entry:
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%fshr = tail call i16 @llvm.fshr.i16(i16 %a, i16 %b, i16 9)
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ret i16 %fshr
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}
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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define i32 @fshr_i32_3rd_arg_const(i32 %a, i32 %b) {
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; CHECK-LABEL: 'fshr_i32_3rd_arg_const'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fshr = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %fshr
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;
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entry:
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%fshr = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 9)
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ret i32 %fshr
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}
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define i32 @fshr_i32_3rd_arg_var(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: 'fshr_i32_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %fshr = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %fshr
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;
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entry:
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%fshr = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
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ret i32 %fshr
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}
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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define i64 @fshr_i64_3rd_arg_const(i64 %a, i64 %b) {
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; CHECK-LABEL: 'fshr_i64_3rd_arg_const'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %fshr = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %fshr
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;
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entry:
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%fshr = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 9)
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ret i64 %fshr
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}
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define i64 @fshr_i64_3rd_arg_var(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: 'fshr_i64_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %fshr = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %fshr
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;
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entry:
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%fshr = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
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ret i64 %fshr
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}
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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define i19 @fshr_i19(i19 %a, i19 %b) {
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; CHECK-LABEL: 'fshr_i19'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %fshr = tail call i19 @llvm.fshr.i19(i19 %a, i19 %b, i19 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i19 %fshr
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;
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entry:
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%fshr = tail call i19 @llvm.fshr.i19(i19 %a, i19 %b, i19 9)
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ret i19 %fshr
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}
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declare i19 @llvm.fshr.i19(i19, i19, i19)
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define <16 x i8> @fshr_v16i8_3rd_arg_vec_const_all_lanes_same(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: 'fshr_v16i8_3rd_arg_vec_const_all_lanes_same'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %fshr
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;
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entry:
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%fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
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ret <16 x i8> %fshr
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}
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define <16 x i8> @fshr_v16i8_3rd_arg_vec_const_lanes_different(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: 'fshr_v16i8_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 9, i8 1, i8 13, i8 7, i8 31, i8 23, i8 43, i8 51, i8 3, i8 3, i8 17, i8 3, i8 11, i8 15, i8 3, i8 3>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %fshr
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;
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entry:
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%fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 9, i8 1, i8 13, i8 7, i8 31, i8 23, i8 43, i8 51, i8 3, i8 3, i8 17, i8 3, i8 11, i8 15, i8 3, i8 3>)
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ret <16 x i8> %fshr
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}
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define <16 x i8> @fshr_v16i8_3rd_arg_var(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: 'fshr_v16i8_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 118 for instruction: %fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %fshr
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;
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entry:
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%fshr = tail call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
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ret <16 x i8> %fshr
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}
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declare <16 x i8> @llvm.fshr.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
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define <8 x i16> @fshr_v8i16_3rd_arg_vec_const_all_lanes_same(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: 'fshr_v8i16_3rd_arg_vec_const_all_lanes_same'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %fshr
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;
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entry:
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%fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)
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ret <8 x i16> %fshr
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}
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define <8 x i16> @fshr_v8i16_3rd_arg_vec_const_lanes_different(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: 'fshr_v8i16_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 1, i16 13, i16 8, i16 7, i16 31, i16 43, i16 51>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %fshr
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;
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entry:
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%fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 1, i16 13, i16 8, i16 7, i16 31, i16 43, i16 51>)
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ret <8 x i16> %fshr
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}
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define <8 x i16> @fshr_v8i16_3rd_arg_var(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: 'fshr_v8i16_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %fshr
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;
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entry:
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%fshr = tail call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
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ret <8 x i16> %fshr
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}
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declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
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define <4 x i32> @fshr_v4i32_3rd_arg_vec_const_all_lanes_same(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: 'fshr_v4i32_3rd_arg_vec_const_all_lanes_same'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %fshr
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;
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entry:
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%fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %fshr
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}
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define <4 x i32> @fshr_v4i32_3rd_arg_vec_const_lanes_different(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: 'fshr_v4i32_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 11, i32 2>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %fshr
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;
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entry:
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%fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 11, i32 2>)
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ret <4 x i32> %fshr
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}
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define <4 x i32> @fshr_v4i32_3rd_arg_var(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: 'fshr_v4i32_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %fshr
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;
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entry:
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%fshr = tail call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
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ret <4 x i32> %fshr
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}
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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define <2 x i64> @fshr_v2i64_3rd_arg_vec_const_all_lanes_same(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: 'fshr_v2i64_3rd_arg_vec_const_all_lanes_same'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %fshr = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 1, i64 1>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %fshr
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;
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entry:
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%fshr = tail call <2 x i64> @llvm.fshr.v4i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 1, i64 1>)
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ret <2 x i64> %fshr
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}
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define <2 x i64> @fshr_v2i64_3rd_arg_vec_const_lanes_different(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: 'fshr_v2i64_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %fshr = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 1, i64 2>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %fshr
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;
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entry:
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%fshr = tail call <2 x i64> @llvm.fshr.v4i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 1, i64 2>)
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ret <2 x i64> %fshr
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}
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define <2 x i64> @fshr_v2i64_3rd_arg_var(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: 'fshr_v2i64_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %fshr = tail call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %fshr
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;
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entry:
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%fshr = tail call <2 x i64> @llvm.fshr.v4i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
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ret <2 x i64> %fshr
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}
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declare <2 x i64> @llvm.fshr.v4i64(<2 x i64>, <2 x i64>, <2 x i64>)
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define <4 x i30> @fshr_v4i30_3rd_arg_var(<4 x i30> %a, <4 x i30> %b, <4 x i30> %c) {
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; CHECK-LABEL: 'fshr_v4i30_3rd_arg_var'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %fshr = tail call <4 x i30> @llvm.fshr.v4i30(<4 x i30> %a, <4 x i30> %b, <4 x i30> %c)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i30> %fshr
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;
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entry:
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%fshr = tail call <4 x i30> @llvm.fshr.v4i30(<4 x i30> %a, <4 x i30> %b, <4 x i30> %c)
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ret <4 x i30> %fshr
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}
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declare <4 x i30> @llvm.fshr.v4i30(<4 x i30>, <4 x i30>, <4 x i30>)
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define <2 x i66> @fshr_v2i66_3rd_arg_vec_const_lanes_different(<2 x i66> %a, <2 x i66> %b) {
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; CHECK-LABEL: 'fshr_v2i66_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %fshr = tail call <2 x i66> @llvm.fshr.v2i66(<2 x i66> %a, <2 x i66> %b, <2 x i66> <i66 1, i66 2>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i66> %fshr
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;
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entry:
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%fshr = tail call <2 x i66> @llvm.fshr.v4i66(<2 x i66> %a, <2 x i66> %b, <2 x i66> <i66 1, i66 2>)
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ret <2 x i66> %fshr
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}
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declare <2 x i66> @llvm.fshr.v4i66(<2 x i66>, <2 x i66>, <2 x i66>)
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define i66 @fshr_i66(i66 %a, i66 %b) {
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; CHECK-LABEL: 'fshr_i66'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %fshr = tail call i66 @llvm.fshr.i66(i66 %a, i66 %b, i66 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i66 %fshr
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;
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entry:
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%fshr = tail call i66 @llvm.fshr.i66(i66 %a, i66 %b, i66 9)
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ret i66 %fshr
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}
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declare i66 @llvm.fshr.i66(i66, i66, i66)
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define <2 x i128> @fshr_v2i128_3rd_arg_vec_const_lanes_different(<2 x i128> %a, <2 x i128> %b) {
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; CHECK-LABEL: 'fshr_v2i128_3rd_arg_vec_const_lanes_different'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %fshr = tail call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 1, i128 2>)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i128> %fshr
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;
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entry:
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%fshr = tail call <2 x i128> @llvm.fshr.v4i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 1, i128 2>)
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ret <2 x i128> %fshr
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}
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declare <2 x i128> @llvm.fshr.v4i128(<2 x i128>, <2 x i128>, <2 x i128>)
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define i128 @fshr_i128(i128 %a, i128 %b) {
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; CHECK-LABEL: 'fshr_i128'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %fshr = tail call i128 @llvm.fshr.i128(i128 %a, i128 %b, i128 9)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i128 %fshr
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;
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entry:
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%fshr = tail call i128 @llvm.fshr.i128(i128 %a, i128 %b, i128 9)
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ret i128 %fshr
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}
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declare i128 @llvm.fshr.i128(i128, i128, i128)
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