ae77aceba5
UniformityAnalysis offers all of the same features and much more, there is no reason left to use the legacy DAs. See RFC: https://discourse.llvm.org/t/rfc-deprecate-divergenceanalysis-legacydivergenceanalysis/69538 - Remove LegacyDivergenceAnalysis.h/.cpp - Remove DivergenceAnalysis.h/.cpp + Unit tests - Remove SyncDependenceAnalysis - it was not a real registered analysis and was only used by DAs - Remove/adjust references to the passes in the docs where applicable - Remove TTI hook associated with those passes. - Move tests to UniformityAnalysis folder. - Remove RUN lines for the DA, leave only the UA ones. - Some tests had to be adjusted/removed depending on how they used the legacy DAs. Reviewed By: foad, sameerds Differential Revision: https://reviews.llvm.org/D148116
109 lines
4.3 KiB
LLVM
109 lines
4.3 KiB
LLVM
; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=tahiti -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s
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; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=gfx908 -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s
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; Make sure nothing crashes on targets with or without AGPRs
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; CHECK-LABEL: for function 'inline_asm_1_sgpr_virtreg_output':
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; CHECK-NOT: DIVERGENT
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define i32 @inline_asm_1_sgpr_virtreg_output() {
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%sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
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ret i32 %sgpr
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}
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; CHECK-LABEL: for function 'inline_asm_1_sgpr_physreg_output':
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; CHECK-NOT: DIVERGENT
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define i32 @inline_asm_1_sgpr_physreg_output() {
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%sgpr = call i32 asm "s_mov_b32 s0, 0", "={s0}"()
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ret i32 %sgpr
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}
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; CHECK-LABEL: for function 'inline_asm_1_vgpr_virtreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
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define i32 @inline_asm_1_vgpr_virtreg_output() {
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%vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
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ret i32 %vgpr
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}
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; CHECK-LABEL: for function 'inline_asm_1_vgpr_physreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
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define i32 @inline_asm_1_vgpr_physreg_output() {
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%vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
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ret i32 %vgpr
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}
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; CHECK-LABEL: for function 'inline_asm_1_agpr_virtreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "; def $0", "=a"()
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define i32 @inline_asm_1_agpr_virtreg_output() {
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%vgpr = call i32 asm "; def $0", "=a"()
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ret i32 %vgpr
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}
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; CHECK-LABEL: for function 'inline_asm_1_agpr_physreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "; def a0", "={a0}"()
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define i32 @inline_asm_1_agpr_physreg_output() {
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%vgpr = call i32 asm "; def a0", "={a0}"()
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ret i32 %vgpr
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}
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; CHECK-LABEL: for function 'inline_asm_2_sgpr_virtreg_output':
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; CHECK-NOT: DIVERGENT
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define void @inline_asm_2_sgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=s"()
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%sgpr0 = extractvalue { i32, i32 } %asm, 0
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%sgpr1 = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr0, ptr addrspace(1) undef
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store i32 %sgpr1, ptr addrspace(1) undef
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ret void
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}
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; One output is SGPR, one is VGPR. Infer divergent for the aggregate, but uniform on the SGPR extract
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; CHECK-LABEL: for function 'inline_asm_sgpr_vgpr_virtreg_output':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_sgpr_vgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()
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%sgpr = extractvalue { i32, i32 } %asm, 0
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%vgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr, ptr addrspace(1) undef
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store i32 %vgpr, ptr addrspace(1) undef
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ret void
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}
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; CHECK-LABEL: for function 'inline_asm_vgpr_sgpr_virtreg_output':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_vgpr_sgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()
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%vgpr = extractvalue { i32, i32 } %asm, 0
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%sgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %vgpr, ptr addrspace(1) undef
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store i32 %sgpr, ptr addrspace(1) undef
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ret void
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}
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; Have an extra output constraint
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; CHECK-LABEL: for function 'multi_sgpr_inline_asm_output_input_constraint':
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; CHECK-NOT: DIVERGENT
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define void @multi_sgpr_inline_asm_output_input_constraint() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=s,s"(i32 1234)
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%sgpr0 = extractvalue { i32, i32 } %asm, 0
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%sgpr1 = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr0, ptr addrspace(1) undef
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store i32 %sgpr1, ptr addrspace(1) undef
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ret void
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}
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; CHECK-LABEL: for function 'inline_asm_vgpr_sgpr_virtreg_output_input_constraint':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_vgpr_sgpr_virtreg_output_input_constraint() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)
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%vgpr = extractvalue { i32, i32 } %asm, 0
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%sgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %vgpr, ptr addrspace(1) undef
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store i32 %sgpr, ptr addrspace(1) undef
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ret void
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}
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