6e54fccede
The instruction-precise, or asynchronous, unwind tables usually take up much more space than the synchronous ones. If a user is concerned about the load size of the program and does not need the features provided with the asynchronous tables, the compiler should be able to generate the more compact variant. This patch changes the generation of CFI instructions for these cases so that they all come in one chunk in the prolog; it emits only one `.cfi_def_cfa*` instruction followed by `.cfi_offset` ones after all stack adjustments and register spills, and avoids generating CFI instructions in the epilog(s) as well as any other exceeding CFI instructions like `.cfi_remember_state` and `.cfi_restore_state`. Effectively, it reverses the effects of D111411 and D114545 on functions with the `uwtable(sync)` attribute. As a side effect, it also restores the behavior on functions that have neither `uwtable` nor `nounwind` attributes. Differential Revision: https://reviews.llvm.org/D153098
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-linux -O0 -tailcallopt < %s | FileCheck %s
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define void @bar() {
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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ret void
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}
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define fastcc i64 @foo(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) {
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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ret i64 %0
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}
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; https://github.com/llvm/llvm-project/issues/60972
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define fastcc i64 @baz() {
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; CHECK-LABEL: baz:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: mov x7, xzr
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; CHECK-NEXT: str xzr, [x8]
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; CHECK-NEXT: mov x0, x7
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; CHECK-NEXT: mov x1, x7
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; CHECK-NEXT: mov x2, x7
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; CHECK-NEXT: mov x3, x7
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; CHECK-NEXT: mov x4, x7
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; CHECK-NEXT: mov x5, x7
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; CHECK-NEXT: mov x6, x7
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
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; CHECK-NEXT: bl bar
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; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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entry:
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%0 = tail call fastcc i64 @foo(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
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call void @bar()
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ret i64 %0
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}
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