db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
79 lines
3.2 KiB
LLVM
79 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK
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; User code intends to execute {pmull, pmull2} instructions on {lower, higher} half of the same vector registers directly.
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; Test that PMULL2 are generated for higher-half operands.
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; The suboptimal code generation fails to use higher-half contents in place; instead, it moves higher-lane contents to lower lane
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; to make use of PMULL everywhere, and generates unnecessary moves.
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define void @test1(ptr %0, ptr %1) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #56824 // =0xddf8
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; CHECK-NEXT: mov w9, #61186 // =0xef02
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; CHECK-NEXT: movk w8, #40522, lsl #16
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; CHECK-NEXT: movk w9, #29710, lsl #16
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; CHECK-NEXT: ldp q0, q1, [x1]
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; CHECK-NEXT: dup v2.2d, x8
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; CHECK-NEXT: fmov d3, x9
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; CHECK-NEXT: pmull v4.1q, v0.1d, v3.1d
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; CHECK-NEXT: pmull v3.1q, v1.1d, v3.1d
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; CHECK-NEXT: pmull2 v0.1q, v0.2d, v2.2d
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; CHECK-NEXT: pmull2 v1.1q, v1.2d, v2.2d
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; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
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; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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%3 = load <2 x i64>, ptr %1
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%4 = getelementptr inbounds <2 x i64>, ptr %1, i64 1
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%5 = load <2 x i64>, ptr %4
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%6 = extractelement <2 x i64> %3, i64 1
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%7 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %6, i64 2655706616)
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%8 = extractelement <2 x i64> %5, i64 1
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%9 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 2655706616)
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%10 = load <2 x i64>, ptr %0
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%11 = getelementptr inbounds i8, ptr %0, i64 16
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%12 = load <2 x i64>, ptr %11
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%13 = extractelement <2 x i64> %3, i64 0
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%14 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %13, i64 1947135746)
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%15 = extractelement <2 x i64> %5, i64 0
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%16 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %15, i64 1947135746)
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%17 = xor <16 x i8> %14, %7
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%18 = xor <16 x i8> %16, %9
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store <16 x i8> %17, ptr %1
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store <16 x i8> %18, ptr %4
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ret void
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}
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; One operand is higher-half of SIMD register, and the other operand is lower-half of another SIMD register.
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; Tests that codegen doesn't generate unnecessary moves.
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define void @test2(ptr %0, <2 x i64> %1, <2 x i64> %2) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup v1.2d, v1.d[0]
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; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%4 = extractelement <2 x i64> %1, i64 1
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%5 = extractelement <2 x i64> %2, i64 0
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%6 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %5)
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store <16 x i8> %6, ptr %0, align 16
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ret void
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}
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; Operand %4 is the higher-half of v2i64, and operand %2 is an input parameter of i64.
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; Test that %2 is duplicated into the proper lane of SIMD directly for optimal codegen.
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define void @test3(ptr %0, <2 x i64> %1, i64 %2) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: dup v1.2d, x1
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; CHECK-NEXT: pmull2 v0.1q, v0.2d, v1.2d
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; CHECK-NEXT: str q0, [x0]
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; CHECK-NEXT: ret
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%4 = extractelement <2 x i64> %1, i64 1
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%5 = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %4, i64 %2)
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store <16 x i8> %5, ptr %0, align 16
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ret void
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}
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declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)
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