db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
457 lines
12 KiB
LLVM
457 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 -o - | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64_be -o - | FileCheck %s --check-prefix=CHECKBE
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define i64 @load32_and16_and(ptr %p, i64 %y) {
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; CHECK-LABEL: load32_and16_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_and:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%ym = and i64 %y, 65535
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%r = and i64 %ym, %xz
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ret i64 %r
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}
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define i64 @load32_and16_andr(ptr %p, i64 %y) {
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; CHECK-LABEL: load32_and16_andr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_andr:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load32_and16_and_sext(ptr %p, i64 %y) {
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; CHECK-LABEL: load32_and16_and_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_and_sext:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = sext i32 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load32_and16_or(ptr %p, i64 %y) {
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; CHECK-LABEL: load32_and16_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: orr w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_or:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: orr w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%a = or i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load32_and16_orr(ptr %p, i64 %y) {
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; CHECK-LABEL: load32_and16_orr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: and x9, x1, #0xffff
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; CHECK-NEXT: orr x0, x9, x8
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_orr:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: and x9, x1, #0xffff
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; CHECKBE-NEXT: orr x0, x9, x8
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%ym = and i64 %y, 65535
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%r = or i64 %ym, %xz
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ret i64 %r
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}
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define i64 @load32_and16_xorm1(ptr %p) {
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; CHECK-LABEL: load32_and16_xorm1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: mvn w8, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_xorm1:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: mvn w8, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%a = xor i64 %xz, -1
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load64_and16(ptr %p, i128 %y) {
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; CHECK-LABEL: load64_and16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: and x0, x2, x8
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load64_and16:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0, #6]
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; CHECKBE-NEXT: and x0, x3, x8
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; CHECKBE-NEXT: ret
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%x = load i64, ptr %p, align 4
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%xz = zext i64 %x to i128
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%a = and i128 %y, %xz
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%t = trunc i128 %a to i64
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%r = and i64 %t, 65535
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ret i64 %r
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}
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define i64 @load16_and16(ptr %p, i64 %y) {
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; CHECK-LABEL: load16_and16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: and x0, x1, x8
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load16_and16:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: and x0, x1, x8
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load16_and8(ptr %p, i64 %y) {
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; CHECK-LABEL: load16_and8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load16_and8:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xff
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 255
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ret i64 %r
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}
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define i64 @load16_and7(ptr %p, i64 %y) {
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; CHECK-LABEL: load16_and7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0x7f
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load16_and7:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0x7f
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 127
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ret i64 %r
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}
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define i64 @load8_and16(ptr %p, i64 %y) {
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; CHECK-LABEL: load8_and16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: and x0, x1, x8
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load8_and16:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrb w8, [x0]
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; CHECKBE-NEXT: and x0, x1, x8
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; CHECKBE-NEXT: ret
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%x = load i8, ptr %p, align 4
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%xz = zext i8 %x to i64
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%a = and i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load8_and16_zext(ptr %p, i8 %y) {
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; CHECK-LABEL: load8_and16_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load8_and16_zext:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrb w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xff
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; CHECKBE-NEXT: ret
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%x = load i8, ptr %p, align 4
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%xz = zext i8 %x to i64
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%yz = zext i8 %y to i64
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%a = and i64 %yz, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load8_and16_sext(ptr %p, i8 %y) {
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; CHECK-LABEL: load8_and16_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: and x0, x1, x8
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load8_and16_sext:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrb w8, [x0]
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; CHECKBE-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECKBE-NEXT: and x0, x1, x8
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; CHECKBE-NEXT: ret
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%x = load i8, ptr %p, align 4
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%xz = zext i8 %x to i64
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%yz = sext i8 %y to i64
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%a = and i64 %yz, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load8_and16_or(ptr %p, i64 %y) {
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; CHECK-LABEL: load8_and16_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrb w8, [x0]
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; CHECK-NEXT: orr w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load8_and16_or:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrb w8, [x0]
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; CHECKBE-NEXT: orr w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i8, ptr %p, align 4
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%xz = zext i8 %x to i64
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%a = or i64 %y, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load16_and8_manyext(ptr %p, i32 %y) {
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; CHECK-LABEL: load16_and8_manyext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: and w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load16_and8_manyext:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: and w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xff
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i32
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%a = and i32 %y, %xz
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%az = zext i32 %a to i64
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%r = and i64 %az, 255
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ret i64 %r
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}
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define i64 @multiple_load(ptr %p, ptr %q) {
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; CHECK-LABEL: multiple_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: multiple_load:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: ldr w9, [x1]
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; CHECKBE-NEXT: and w8, w9, w8
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; CHECKBE-NEXT: and x0, x8, #0xff
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i64
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%y = load i32, ptr %q, align 4
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%yz = zext i32 %y to i64
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%a = and i64 %yz, %xz
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%r = and i64 %a, 255
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ret i64 %r
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}
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define i64 @multiple_load_or(ptr %p, ptr %q) {
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; CHECK-LABEL: multiple_load_or:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w8, [x0]
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: and x0, x8, #0xff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: multiple_load_or:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldrh w8, [x0]
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; CHECKBE-NEXT: ldr w9, [x1]
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; CHECKBE-NEXT: orr w8, w9, w8
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; CHECKBE-NEXT: and x0, x8, #0xff
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; CHECKBE-NEXT: ret
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%x = load i16, ptr %p, align 4
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%xz = zext i16 %x to i64
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%y = load i32, ptr %q, align 4
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%yz = zext i32 %y to i64
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%a = or i64 %yz, %xz
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%r = and i64 %a, 255
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ret i64 %r
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}
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define i64 @load32_and16_zexty(ptr %p, i32 %y) {
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; CHECK-LABEL: load32_and16_zexty:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: orr w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_zexty:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: orr w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%yz = zext i32 %y to i64
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%a = or i64 %yz, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define i64 @load32_and16_sexty(ptr %p, i32 %y) {
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; CHECK-LABEL: load32_and16_sexty:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: orr w8, w1, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: load32_and16_sexty:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ldr w8, [x0]
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; CHECKBE-NEXT: orr w8, w1, w8
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; CHECKBE-NEXT: and x0, x8, #0xffff
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; CHECKBE-NEXT: ret
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%x = load i32, ptr %p, align 4
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%xz = zext i32 %x to i64
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%yz = sext i32 %y to i64
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%a = or i64 %yz, %xz
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%r = and i64 %a, 65535
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ret i64 %r
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}
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define zeroext i1 @bigger(ptr nocapture readonly %c, ptr nocapture readonly %e, i64 %d, i64 %p1) {
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; CHECK-LABEL: bigger:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldrb w8, [x1, x2]
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; CHECK-NEXT: ldrb w9, [x0, x2]
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; CHECK-NEXT: and w10, w3, #0x7
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; CHECK-NEXT: mov w11, #8 // =0x8
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; CHECK-NEXT: sub w10, w11, w10
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; CHECK-NEXT: eor w8, w8, w9
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; CHECK-NEXT: mov w9, #5 // =0x5
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; CHECK-NEXT: lsr w8, w8, w10
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; CHECK-NEXT: tst w8, w9
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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;
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; CHECKBE-LABEL: bigger:
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; CHECKBE: // %bb.0: // %entry
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; CHECKBE-NEXT: ldrb w8, [x1, x2]
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; CHECKBE-NEXT: ldrb w9, [x0, x2]
|
|
; CHECKBE-NEXT: and w10, w3, #0x7
|
|
; CHECKBE-NEXT: mov w11, #8 // =0x8
|
|
; CHECKBE-NEXT: sub w10, w11, w10
|
|
; CHECKBE-NEXT: eor w8, w8, w9
|
|
; CHECKBE-NEXT: mov w9, #5 // =0x5
|
|
; CHECKBE-NEXT: lsr w8, w8, w10
|
|
; CHECKBE-NEXT: tst w8, w9
|
|
; CHECKBE-NEXT: cset w0, eq
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|
; CHECKBE-NEXT: ret
|
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entry:
|
|
%0 = trunc i64 %p1 to i16
|
|
%1 = and i16 %0, 7
|
|
%sh_prom = sub nuw nsw i16 8, %1
|
|
%shl = shl nuw nsw i16 5, %sh_prom
|
|
%arrayidx = getelementptr inbounds i8, ptr %c, i64 %d
|
|
%2 = load i8, ptr %arrayidx, align 1
|
|
%3 = and i16 %shl, 255
|
|
%conv2 = zext i16 %3 to i32
|
|
%arrayidx3 = getelementptr inbounds i8, ptr %e, i64 %d
|
|
%4 = load i8, ptr %arrayidx3, align 1
|
|
%5 = xor i8 %4, %2
|
|
%6 = zext i8 %5 to i32
|
|
%7 = and i32 %6, %conv2
|
|
%cmp.not = icmp eq i32 %7, 0
|
|
ret i1 %cmp.not
|
|
}
|