6e85db7293
The outer signext_inreg is redundant in the following:
Fold (signext_inreg (extract_subvector (zext|anyext|sext iN_value to _) _) from iN)
-> (extract_subvector (signext iN_value to iM))
Tests are precommitted and clone those by analogy from the AND case in
the same file. Add a negative test to check extension width is handled
correctly.
This patch supersedes D130700.
Differential Revision: https://reviews.llvm.org/D131503
125 lines
5.1 KiB
LLVM
125 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK
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define <2 x i32> @and_extract_zext_idx0(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: and_extract_zext_idx0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%and = and <2 x i32> %extract, <i32 65535, i32 65535>
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ret <2 x i32> %and
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}
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define <4 x i16> @and_extract_sext_idx0(<8 x i8> %vec) nounwind {
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; CHECK-LABEL: and_extract_sext_idx0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
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%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
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ret <4 x i16> %and
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}
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define <2 x i32> @and_extract_zext_idx2(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: and_extract_zext_idx2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
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%and = and <2 x i32> %extract, <i32 65535, i32 65535>
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ret <2 x i32> %and
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}
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define <4 x i16> @and_extract_sext_idx4(<8 x i8> %vec) nounwind {
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; CHECK-LABEL: and_extract_sext_idx4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
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%and = and <4 x i16> %extract, <i16 255, i16 255, i16 255, i16 255>
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ret <4 x i16> %and
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}
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define <2 x i32> @sext_extract_zext_idx0(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: sext_extract_zext_idx0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>
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ret <2 x i32> %sext_inreg
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}
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; Negative test, combine should not fire if sign extension is for a different width.
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define <2 x i32> @sext_extract_zext_idx0_negtest(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: sext_extract_zext_idx0_negtest:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: shl v0.2s, v0.2s, #17
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; CHECK-NEXT: sshr v0.2s, v0.2s, #17
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 17, i32 17>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 17, i32 17>
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ret <2 x i32> %sext_inreg
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}
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define <4 x i16> @sext_extract_sext_idx0(<8 x i8> %vec) nounwind {
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; CHECK-LABEL: sext_extract_sext_idx0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 0)
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%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
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%sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>
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ret <4 x i16> %sext_inreg
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}
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define <2 x i32> @sext_extract_zext_idx2(<4 x i16> %vec) nounwind {
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; CHECK-LABEL: sext_extract_zext_idx2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%zext = zext <4 x i16> %vec to <4 x i32>
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%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 2)
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%sext_inreg_step0 = shl <2 x i32> %extract, <i32 16, i32 16>
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%sext_inreg = ashr <2 x i32> %sext_inreg_step0, <i32 16, i32 16>
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ret <2 x i32> %sext_inreg
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}
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define <4 x i16> @sext_extract_sext_idx4(<8 x i8> %vec) nounwind {
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; CHECK-LABEL: sext_extract_sext_idx4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%sext = sext <8 x i8> %vec to <8 x i16>
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%extract = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %sext, i64 4)
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%sext_inreg_step0 = shl <4 x i16> %extract, <i16 8, i16 8, i16 8, i16 8>
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%sext_inreg = ashr <4 x i16> %sext_inreg_step0, <i16 8, i16 8, i16 8, i16 8>
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ret <4 x i16> %sext_inreg
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}
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declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
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declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
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