42b3419339
As far as I can tell FeatureLSLFast was originally added to specify that a lsl of <= 3 was cheap when folded into an addressing operand, so should override the one-use checks usually intended to make sure we don't perform redundant work. At a later point it also came to also mean that add x0, x1, x2, lsl N with N <= 4 was cheap, in that it took a single cycle not multiple cycles that more complex adds usually take. This patch splits those two concepts out into separate subtarget features. The biggest change is the change to AArch64DAGToDAGISel::isWorthFoldingALU, making ALU operations now produce a ADDWrs if the shift is <= 4. Otherwise the patch is mostly an NFC as it tries to keep the subtarget features the same for each cpu. I believe that the Arm OoO CPUs should eventually be changed to a new subtarget feature that specifies that a shift of 2 or 3 with any extend should be treated as cheap (just not shifts of 1 or 4). Differential Revision: https://reviews.llvm.org/D157982
130 lines
3.7 KiB
LLVM
130 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SLOW
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+alu-lsl-fast | FileCheck %s --check-prefixes=CHECK,CHECK-FAST
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define i32 @testmul3(i32 noundef %x, i32 noundef %y, i32 noundef %z) {
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; CHECK-SLOW-LABEL: testmul3:
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; CHECK-SLOW: // %bb.0: // %entry
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; CHECK-SLOW-NEXT: lsl w8, w0, #3
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; CHECK-SLOW-NEXT: add w9, w8, w1
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; CHECK-SLOW-NEXT: add w8, w8, w2
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; CHECK-SLOW-NEXT: mul w0, w8, w9
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; CHECK-SLOW-NEXT: ret
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;
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; CHECK-FAST-LABEL: testmul3:
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; CHECK-FAST: // %bb.0: // %entry
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; CHECK-FAST-NEXT: add w8, w1, w0, lsl #3
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; CHECK-FAST-NEXT: add w9, w2, w0, lsl #3
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; CHECK-FAST-NEXT: mul w0, w9, w8
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; CHECK-FAST-NEXT: ret
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entry:
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%shl = shl i32 %x, 3
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%add = add nsw i32 %shl, %y
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%add2 = add nsw i32 %shl, %z
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%mul = mul nsw i32 %add2, %add
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ret i32 %mul
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}
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define i32 @testvar(i32 noundef %x, i32 noundef %y, i32 noundef %z, i32 %zz) {
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; CHECK-LABEL: testvar:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: lsl w8, w0, w3
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; CHECK-NEXT: add w9, w8, w1
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; CHECK-NEXT: add w8, w8, w2
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; CHECK-NEXT: mul w0, w8, w9
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; CHECK-NEXT: ret
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entry:
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%shl = shl i32 %x, %zz
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%add = add nsw i32 %shl, %y
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%add2 = add nsw i32 %shl, %z
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%mul = mul nsw i32 %add2, %add
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ret i32 %mul
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}
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define i32 @testmul5(i32 noundef %x, i32 noundef %y, i32 noundef %z) {
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; CHECK-LABEL: testmul5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: lsl w8, w0, #5
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; CHECK-NEXT: add w9, w8, w1
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; CHECK-NEXT: add w8, w8, w2
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; CHECK-NEXT: mul w0, w8, w9
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; CHECK-NEXT: ret
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entry:
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%shl = shl i32 %x, 5
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%add = add nsw i32 %shl, %y
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%add2 = add nsw i32 %shl, %z
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%mul = mul nsw i32 %add2, %add
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ret i32 %mul
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}
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define i64 @testsext3(i32 noundef %x, i64 noundef %y, i64 noundef %z) {
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; CHECK-LABEL: testsext3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfiz x8, x0, #3, #32
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; CHECK-NEXT: add x9, x8, x1
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; CHECK-NEXT: add x8, x8, x2
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; CHECK-NEXT: mul x0, x9, x8
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; CHECK-NEXT: ret
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entry:
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%conv = sext i32 %x to i64
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%shl = shl nsw i64 %conv, 3
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%add = add nsw i64 %shl, %y
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%add3 = add nsw i64 %shl, %z
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%mul = mul nsw i64 %add, %add3
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ret i64 %mul
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}
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define i64 @testzext3(i32 noundef %x, i64 noundef %y, i64 noundef %z) {
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; CHECK-LABEL: testzext3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: ubfiz x8, x0, #3, #32
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; CHECK-NEXT: add x9, x8, x1
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; CHECK-NEXT: add x8, x8, x2
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; CHECK-NEXT: mul x0, x9, x8
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; CHECK-NEXT: ret
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entry:
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%conv = zext i32 %x to i64
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%shl = shl nsw i64 %conv, 3
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%add = add nsw i64 %shl, %y
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%add3 = add nsw i64 %shl, %z
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%mul = mul nsw i64 %add, %add3
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ret i64 %mul
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}
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define i64 @test3sext(i32 noundef %x, i64 noundef %y, i64 noundef %z) {
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; CHECK-LABEL: test3sext:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: lsl w8, w0, #3
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; CHECK-NEXT: sxtw x8, w8
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; CHECK-NEXT: add x9, x8, x1
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; CHECK-NEXT: add x8, x8, x2
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; CHECK-NEXT: mul x0, x9, x8
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; CHECK-NEXT: ret
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entry:
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%shl = shl i32 %x, 3
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%conv = sext i32 %shl to i64
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%add = add nsw i64 %conv, %y
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%add3 = add nsw i64 %conv, %z
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%mul = mul nsw i64 %add, %add3
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ret i64 %mul
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}
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define i64 @test3zext(i32 noundef %x, i64 noundef %y, i64 noundef %z) {
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; CHECK-LABEL: test3zext:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: lsl w8, w0, #3
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; CHECK-NEXT: add x9, x8, x1
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; CHECK-NEXT: add x8, x8, x2
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; CHECK-NEXT: mul x0, x9, x8
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; CHECK-NEXT: ret
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entry:
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%shl = shl i32 %x, 3
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%conv = zext i32 %shl to i64
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%add = add nsw i64 %conv, %y
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%add3 = add nsw i64 %conv, %z
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%mul = mul nsw i64 %add, %add3
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ret i64 %mul
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}
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